boards: nrf54h20dk: Merge iron variants into the base variants

This replaces the legacy SDFW compatible board configuration with the
IronSide SE compatible one, thus removing support for running samples
and tests on nRF54H20 devices with the old firmware.

All applications are expected to work on `nrf54h20dk/nrf54h20/cpuapp`
out of the box. For other board targets, all applications are expected
to boot, but may require additional peripheral configuration in UICR.
Build system support for the new UICR format is to be added separately.

Co-authored-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>

boards/nordic/nrf54h20dk/Kconfig.defconfig

@@ -12,6 +12,18 @@ config BT_HCI_IPC
 config MAX_THREAD_BYTES
 	default 3 if USERSPACE
 
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+if !USE_DT_CODE_PARTITION
+
+# Application core firmware must start at this offset when not using MCUboot.
+# However, the default 'zephyr,code-partition' in DT is set for MCUboot.
+config FLASH_LOAD_OFFSET
+	default $(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition)
+
+endif # !USE_DT_CODE_PARTITION
+
 endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP
 
 if BOARD_NRF54H20DK_NRF54H20_CPURAD
@@ -19,21 +31,7 @@ if BOARD_NRF54H20DK_NRF54H20_CPURAD
 config MAX_THREAD_BYTES
 	default 3 if USERSPACE
 
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
 endif # BOARD_NRF54H20DK_NRF54H20_CPURAD
-
-if BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON
-
-config ROM_START_OFFSET
-	default 0x800 if BOOTLOADER_MCUBOOT
-
-config FLASH_LOAD_OFFSET
-	default 0x2c000 if !USE_DT_CODE_PARTITION
-
-endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON
-
-if BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON
-
-config ROM_START_OFFSET
-	default 0x800 if BOOTLOADER_MCUBOOT
-
-endif # BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON

boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk

@@ -2,13 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_NRF54H20DK
-	select SOC_NRF54H20_CPUAPP if (BOARD_NRF54H20DK_NRF54H20_CPUAPP || \
+	select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP
-				       BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON)
+	select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD
-	select SOC_NRF54H20_CPURAD if (BOARD_NRF54H20DK_NRF54H20_CPURAD || \
-				       BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)
 	select SOC_NRF54H20_CPUPPR if (BOARD_NRF54H20DK_NRF54H20_CPUPPR || \
 				       BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP)
 	select SOC_NRF54H20_CPUFLPR if (BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \
 				        BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP)
-	select SOC_NRF54H20_IRON if (BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON || \
-				       BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)

boards/nordic/nrf54h20dk/board.cmake

@@ -2,10 +2,7 @@
 
 include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
 
-if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
+if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD)
-   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR
-   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON OR
-   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)
   if(CONFIG_SOC_NRF54H20_CPUAPP)
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuapp.JLinkScript)
   else()
@@ -17,7 +14,7 @@ if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
 endif()
 
 if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUFLPR)
-  if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR)
+  if(CONFIG_SOC_NRF54H20_CPUPPR)
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuppr.JLinkScript)
   else()
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuflpr.JLinkScript)

boards/nordic/nrf54h20dk/board.yml

@@ -9,10 +9,6 @@ board:
       cpucluster: cpuppr
     - name: xip
       cpucluster: cpuflpr
-    - name: iron
-      cpucluster: cpuapp
-    - name: iron
-      cpucluster: cpurad
   revision:
     format: major.minor.patch
     default: "0.9.0"

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi

@@ -7,17 +7,17 @@
 / {
 	ipc {
 		cpusec_cpuapp_ipc: ipc-1-2 {
-			compatible = "zephyr,ipc-icmsg";
+			compatible = "nordic,ironside-call";
 			status = "disabled";
-			dcache-alignment = <32>;
+			memory-region = <&cpusec_cpuapp_ipc_shm>;
 			mboxes = <&cpusec_bellboard 12>,
 				 <&cpuapp_bellboard 0>;
 		};
 
 		cpusec_cpurad_ipc: ipc-1-3 {
-			compatible = "zephyr,ipc-icmsg";
+			compatible = "nordic,ironside-call";
 			status = "disabled";
-			dcache-alignment = <32>;
+			memory-region = <&cpusec_cpurad_ipc_shm>;
 			mboxes = <&cpusec_bellboard 18>,
 				 <&cpurad_bellboard 0>;
 		};

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi

@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/* This file is to be merged with the original ipc_conf.dtsi in the future. */
-
-/ {
-	ipc {
-		/delete-node/ ipc-1-2;
-		/delete-node/ ipc-1-3;
-
-		cpusec_cpuapp_ipc: ipc-1-2 {
-			compatible = "nordic,ironside-call";
-			memory-region = <&cpusec_cpuapp_ipc_shm>;
-			mboxes = <&cpusec_bellboard 12>,
-				 <&cpuapp_bellboard 0>;
-			status = "disabled";
-		};
-
-		cpusec_cpurad_ipc: ipc-1-3 {
-			compatible = "nordic,ironside-call";
-			memory-region = <&cpusec_cpurad_ipc_shm>;
-			mboxes = <&cpusec_bellboard 18>,
-				 <&cpurad_bellboard 0>;
-			status = "disabled";
-		};
-	};
-};

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi

@@ -16,14 +16,6 @@
 			#size-cells = <1>;
 			ranges = <0x0 0x2f010000 0x41000>;
 
-			cpusec_cpuapp_ipc_shm: memory@0 {
-				reg = <0x0 DT_SIZE_K(2)>;
-			};
-
-			cpuapp_cpusec_ipc_shm: memory@800 {
-				reg = <0x800 DT_SIZE_K(2)>;
-			};
-
 			cpuapp_data: memory@1000 {
 				reg = <0x1000 DT_SIZE_K(256)>;
 			};
@@ -37,14 +29,6 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x0 0x2f051000 0x1000>;
-
-			cpusec_cpurad_ipc_shm: memory@0 {
-				reg = <0x0 DT_SIZE_K(2)>;
-			};
-
-			cpurad_cpusec_ipc_shm: memory@800 {
-				reg = <0x800 DT_SIZE_K(2)>;
-			};
 		};
 
 		etr_buf_ram0x_region: memory@2f0be000 {
@@ -81,20 +65,44 @@
 			};
 		};
 
-		cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
+		cpuapp_cpusys_ipc_shm: memory@2f88f600 {
-			reg = <0x2f88fce0 0x80>;
+			reg = <0x2f88f600 0x80>;
 		};
 
-		cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
+		cpusys_cpuapp_ipc_shm: memory@2f88f680 {
-			reg = <0x2f88fd60 0x80>;
+			reg = <0x2f88f680 0x80>;
 		};
 
-		cpurad_cpusys_ipc_shm: memory@2f88fe00 {
+		cpurad_cpusys_ipc_shm: memory@2f88f700 {
-			reg = <0x2f88fe00 0x80>;
+			reg = <0x2f88f700 0x80>;
 		};
 
-		cpusys_cpurad_ipc_shm: memory@2f88fe80 {
+		cpusys_cpurad_ipc_shm: memory@2f88f780 {
-			reg = <0x2f88fe80 0x80>;
+			reg = <0x2f88f780 0x80>;
+		};
+
+		cpusec_cpurad_ipc_shm: memory@2f88f800 {
+			reg = <0x2f88f800 0x80>;
+		};
+
+		cpurad_ironside_se_event_report: memory@2f88f880 {
+			reg = <0x2f88f880 0x100>;
+		};
+
+		cpurad_ironside_se_boot_report: memory@2f88f980 {
+			reg = <0x2f88f980 0x200>;
+		};
+
+		cpusec_cpuapp_ipc_shm: memory@2f88fb80 {
+			reg = <0x2f88fb80 0x80>;
+		};
+
+		cpuapp_ironside_se_event_report: memory@2f88fc00 {
+			reg = <0x2f88fc00 0x100>;
+		};
+
+		cpuapp_ironside_se_boot_report: memory@2f88fd00 {
+			reg = <0x2f88fd00 0x200>;
 		};
 
 		/*
@@ -187,27 +195,21 @@
 };
 
 &mram1x {
-	cpurad_rx_partitions: cpurad-rx-partitions {
+	partitions {
-		compatible = "nordic,owned-partitions", "fixed-partitions";
+		compatible = "fixed-partitions";
-		status = "disabled";
-		nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RXS>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpurad_slot0_partition: partition@54000 {
+		cpuapp_boot_partition: partition@2c000 {
-			reg = <0x54000 DT_SIZE_K(256)>;
+			reg = <0x2c000 DT_SIZE_K(64)>;
 		};
-	};
 
-	cpuapp_rx_partitions: cpuapp-rx-partitions {
+		cpuapp_slot0_partition: partition@3c000 {
-		compatible = "nordic,owned-partitions", "fixed-partitions";
+			reg = <0x3c000 DT_SIZE_K(336)>;
-		status = "disabled";
+		};
-		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
-		#address-cells = <1>;
-		#size-cells = <1>;
 
-		cpuapp_slot0_partition: partition@94000 {
+		cpurad_slot0_partition: partition@90000 {
-			reg = <0x94000 DT_SIZE_K(320)>;
+			reg = <0x90000 DT_SIZE_K(336)>;
 		};
 
 		cpuppr_code_partition: partition@e4000 {
@@ -217,21 +219,17 @@
 		cpuflpr_code_partition: partition@f4000 {
 			reg = <0xf4000 DT_SIZE_K(48)>;
 		};
-	};
 
-	cpuapp_rw_partitions: cpuapp-rw-partitions {
+		cpuapp_slot1_partition: partition@100000 {
-		compatible = "nordic,owned-partitions", "fixed-partitions";
+			reg = <0x100000 DT_SIZE_K(336)>;
-		status = "disabled";
-		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		dfu_partition: partition@100000 {
-			reg = < 0x100000 DT_SIZE_K(908) >;
 		};
 
-		storage_partition: partition@1e3000 {
+		cpurad_slot1_partition: partition@154000 {
-			reg = < 0x1e3000 DT_SIZE_K(40) >;
+			reg = <0x154000 DT_SIZE_K(336)>;
+		};
+
+		storage_partition: partition@1a8000 {
+			reg = <0x1a8000 DT_SIZE_K(40)>;
 		};
 	};
 };

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map_iron.dtsi

@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/* This file is to be merged with the original memory_map.dtsi in the future.
- * The following nodes will be replaced:
- */
-/delete-node/ &cpuapp_cpusec_ipc_shm;
-/delete-node/ &cpuapp_cpusys_ipc_shm;
-/delete-node/ &cpurad_cpusec_ipc_shm;
-/delete-node/ &cpurad_cpusys_ipc_shm;
-/delete-node/ &cpusec_cpuapp_ipc_shm;
-/delete-node/ &cpusec_cpurad_ipc_shm;
-/delete-node/ &cpusys_cpuapp_ipc_shm;
-/delete-node/ &cpusys_cpurad_ipc_shm;
-/delete-node/ &cpuapp_rw_partitions;
-/delete-node/ &cpuapp_rx_partitions;
-/delete-node/ &cpurad_rx_partitions;
-
-/ {
-	reserved-memory {
-		cpuapp_cpusys_ipc_shm: memory@2f88f600 {
-			reg = <0x2f88f600 0x80>;
-		};
-
-		cpusys_cpuapp_ipc_shm: memory@2f88f680 {
-			reg = <0x2f88f680 0x80>;
-		};
-
-		cpurad_cpusys_ipc_shm: memory@2f88f700 {
-			reg = <0x2f88f700 0x80>;
-		};
-
-		cpusys_cpurad_ipc_shm: memory@2f88f780 {
-			reg = <0x2f88f780 0x80>;
-		};
-
-		cpusec_cpurad_ipc_shm: memory@2f88f800 {
-			reg = <0x2f88f800 0x80>;
-		};
-
-		cpurad_ironside_se_event_report: memory@2f88f880 {
-			reg = <0x2f88f880 0x100>;
-		};
-
-		cpurad_ironside_se_boot_report: memory@2f88f980 {
-			reg = <0x2f88f980 0x200>;
-		};
-
-		cpusec_cpuapp_ipc_shm: memory@2f88fb80 {
-			reg = <0x2f88fb80 0x80>;
-		};
-
-		cpuapp_ironside_se_event_report: memory@2f88fc00 {
-			reg = <0x2f88fc00 0x100>;
-		};
-
-		cpuapp_ironside_se_boot_report: memory@2f88fd00 {
-			reg = <0x2f88fd00 0x200>;
-		};
-	};
-};
-
-&mram1x {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		cpuapp_boot_partition: partition@2c000 {
-			reg = <0x2c000 DT_SIZE_K(64)>;
-		};
-
-		cpuapp_slot0_partition: partition@3c000 {
-			reg = <0x3c000 DT_SIZE_K(336)>;
-		};
-
-		cpurad_slot0_partition: partition@90000 {
-			reg = <0x90000 DT_SIZE_K(336)>;
-		};
-
-		cpuppr_code_partition: partition@e4000 {
-			reg = <0xe4000 DT_SIZE_K(64)>;
-		};
-
-		cpuflpr_code_partition: partition@f4000 {
-			reg = <0xf4000 DT_SIZE_K(48)>;
-		};
-
-		cpuapp_slot1_partition: partition@100000 {
-			reg = <0x100000 DT_SIZE_K(336)>;
-		};
-
-		cpurad_slot1_partition: partition@154000 {
-			reg = <0x154000 DT_SIZE_K(336)>;
-		};
-
-		storage_partition: partition@1a8000 {
-			reg = <0x1a8000 DT_SIZE_K(40)>;
-		};
-	};
-};

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts

@@ -18,10 +18,11 @@
 
 	chosen {
 		zephyr,console = &uart136;
-		zephyr,code-partition = &cpuapp_slot0_partition;
+		zephyr,code-partition = &slot0_partition;
 		zephyr,flash = &mram1x;
 		zephyr,sram = &cpuapp_data;
 		zephyr,shell-uart = &uart136;
+		zephyr,uart-mcumgr = &uart136;
 		zephyr,ieee802154 = &cpuapp_ieee802154;
 		zephyr,bt-hci = &bt_hci_ipc0;
 		nordic,802154-spinel-ipc = &ipc0;
@@ -145,8 +146,6 @@
 &cpusec_cpuapp_ipc {
 	status = "okay";
 	mbox-names = "tx", "rx";
-	tx-region = <&cpuapp_cpusec_ipc_shm>;
-	rx-region = <&cpusec_cpuapp_ipc_shm>;
 };
 
 &cpusec_bellboard {
@@ -190,12 +189,26 @@ ipc0: &cpuapp_cpurad_ipc {
 	status = "okay";
 };
 
-&cpuapp_rx_partitions {
+ironside_se_boot_report: &cpuapp_ironside_se_boot_report {};
-	status = "okay";
+
+boot_partition: &cpuapp_boot_partition {
+	label = "mcuboot";
 };
 
-&cpuapp_rw_partitions {
+slot0_partition: &cpuapp_slot0_partition {
-	status = "okay";
+	label = "image-0";
+};
+
+slot1_partition: &cpuapp_slot1_partition {
+	label = "image-1";
+};
+
+slot2_partition: &cpurad_slot0_partition {
+	label = "image-2";
+};
+
+slot3_partition: &cpurad_slot1_partition {
+	label = "image-3";
 };
 
 &cpuppr_vpr {

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig

@@ -8,8 +8,6 @@ CONFIG_SERIAL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 
-CONFIG_USE_DT_CODE_PARTITION=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts

@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "nrf54h20dk_nrf54h20_cpuapp.dts"
-#include "nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi"
-#include "nrf54h20dk_nrf54h20-memory_map_iron.dtsi"
-
-/delete-node/ &cpusec_cpurad_ipc;
-
-/ {
-	chosen {
-		zephyr,code-partition = &slot0_partition;
-		zephyr,uart-mcumgr = &uart136;
-	};
-};
-
-&cpusec_cpuapp_ipc {
-	mbox-names = "tx", "rx";
-	status = "okay";
-};
-
-ironside_se_boot_report: &cpuapp_ironside_se_boot_report {};
-
-boot_partition: &cpuapp_boot_partition {
-	label = "mcuboot";
-};
-
-slot0_partition: &cpuapp_slot0_partition {
-	label = "image-0";
-};
-
-slot1_partition: &cpuapp_slot1_partition {
-	label = "image-1";
-};
-
-slot2_partition: &cpurad_slot0_partition {
-	label = "image-2";
-};
-
-slot3_partition: &cpurad_slot1_partition {
-	label = "image-3";
-};

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_0_9_0.yaml

@@ -1,25 +0,0 @@
-# Copyright (c) 2025 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-identifier: nrf54h20dk/nrf54h20/cpuapp/iron
-name: nRF54H20-DK-nRF54H20-Application (IronSide compatible) (revision 0.9.0)
-type: mcu
-arch: arm
-toolchain:
-  - gnuarmemb
-  - xtools
-  - zephyr
-sysbuild: true
-ram: 256
-flash: 480
-supported:
-  - adc
-  - can
-  - counter
-  - gpio
-  - i2c
-  - pwm
-  - retained_mem
-  - spi
-  - watchdog
-  - usbd

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_defconfig

@@ -1,26 +0,0 @@
-# Copyright (c) 2025 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-# Enable UART driver
-CONFIG_SERIAL=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Enable MPU
-CONFIG_ARM_MPU=y
-
-# MPU-based null-pointer dereferencing detection cannot be applied
-# as the (0x0 - 0x400) region is unmapped for this target.
-CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
-
-# Enable cache
-CONFIG_CACHE_MANAGEMENT=y
-CONFIG_EXTERNAL_CACHE=y
-
-# Enable GPIO
-CONFIG_GPIO=y
-
-# UICR generation is not supported, and when reintroduced will not use nrf-regtool.
-CONFIG_NRF_REGTOOL_GENERATE_UICR=n

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts

@@ -24,6 +24,7 @@
 		zephyr,flash = &mram1x;
 		zephyr,sram = &cpurad_ram0;
 		zephyr,shell-uart = &uart135;
+		zephyr,uart-mcumgr = &uart135;
 		zephyr,ieee802154 = &cpurad_ieee802154;
 		zephyr,bt-hci-ipc = &ipc0;
 		nordic,802154-spinel-ipc = &ipc0;
@@ -62,8 +63,6 @@
 &cpusec_cpurad_ipc {
 	status = "okay";
 	mbox-names = "tx", "rx";
-	tx-region = <&cpurad_cpusec_ipc_shm>;
-	rx-region = <&cpusec_cpurad_ipc_shm>;
 };
 
 &cpusec_bellboard {
@@ -90,8 +89,12 @@ ipc0: &cpuapp_cpurad_ipc {
 	status = "okay";
 };
 
-&cpurad_rx_partitions {
+slot0_partition: &cpurad_slot0_partition {
-	status = "okay";
+	label = "image-0";
+};
+
+slot1_partition: &cpurad_slot1_partition {
+	label = "image-1";
 };
 
 &grtc {

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron.dts

@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "nrf54h20dk_nrf54h20_cpurad.dts"
-#include "nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi"
-#include "nrf54h20dk_nrf54h20-memory_map_iron.dtsi"
-
-/ {
-	chosen {
-		zephyr,code-partition = &cpurad_slot0_partition;
-		zephyr,uart-mcumgr = &uart135;
-	};
-};
-
-&cpusec_cpurad_ipc {
-	mbox-names = "tx", "rx";
-	status = "okay";
-};
-
-slot0_partition: &cpurad_slot0_partition {
-	label = "image-0";
-};
-
-slot1_partition: &cpurad_slot1_partition {
-	label = "image-1";
-};

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron_0_9_0.yaml

@@ -1,20 +0,0 @@
-# Copyright (c) 2025 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-identifier: nrf54h20dk/nrf54h20/cpurad/iron
-name: nRF54H20-DK-nRF54H20-Radio (IronSide SE compatible) (revision 0.9.0)
-type: mcu
-arch: arm
-toolchain:
-  - gnuarmemb
-  - xtools
-  - zephyr
-sysbuild: true
-ram: 192
-flash: 336
-supported:
-  - counter
-  - gpio
-  - pwm
-  - retained_mem
-  - spi

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron_defconfig

@@ -1,25 +0,0 @@
-# Copyright (c) 2025 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-# Enable UART driver
-CONFIG_SERIAL=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-CONFIG_USE_DT_CODE_PARTITION=y
-
-# Enable MPU
-CONFIG_ARM_MPU=y
-
-# MPU-based null-pointer dereferencing detection cannot be applied
-# as the (0x0 - 0x400) region is unmapped for this target.
-CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
-
-# Enable cache
-CONFIG_CACHE_MANAGEMENT=y
-CONFIG_EXTERNAL_CACHE=y
-
-# UICR generation is not supported, and when reintroduced will not use nrf-regtool.
-CONFIG_NRF_REGTOOL_GENERATE_UICR=n

dts/vendor/nordic/nrf54h20.dtsi

@@ -152,10 +152,6 @@
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
-
-		suit_storage_partition: memory@e1ed000 {
-			reg = <0xe1ed000 DT_SIZE_K(20)>;
-		};
 	};
 
 	clocks {

samples/boards/nordic/nrf_ironside/update/README.rst

@@ -25,8 +25,8 @@ The update procedure works as follows:
 
 Once the operation has completed, you can read the boot report to verify that the update has taken place.
 
-Building and running the application for nrf54h20dk/nrf54h20/cpuapp/iron
+Building and running the application for nrf54h20dk/nrf54h20/cpuapp
-************************************************************************
+*******************************************************************
 
 .. note::
    You can use this application only when there is already a version of IronSide SE installed on the device.
@@ -55,7 +55,7 @@ Building and running the application for nrf54h20dk/nrf54h20/cpuapp/iron
 
    .. zephyr-app-commands::
       :zephyr-app: samples/boards/nordic/nrf_ironside/update
-      :board: nrf54h20dk/nrf54h20/cpuapp/iron
+      :board: nrf54h20dk/nrf54h20/cpuapp
       :goals: flash
 
 #. Trigger a reset:

samples/boards/nordic/nrf_ironside/update/sample.yaml

@@ -5,8 +5,8 @@ common:
   build_only: true
   tags: nrf_ironside
   integration_platforms:
-    - nrf54h20dk/nrf54h20/cpuapp/iron
+    - nrf54h20dk/nrf54h20/cpuapp
 
 tests:
   sample.boards.nordic.nrf_ironside.update:
-    platform_allow: nrf54h20dk/nrf54h20/cpuapp/iron
+    platform_allow: nrf54h20dk/nrf54h20/cpuapp

samples/drivers/counter/alarm/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay

@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: Apache-2.0 */
-
-#include "nrf54h20dk_nrf54h20_common.dtsi"

samples/drivers/mbox/sample.yaml

@@ -65,6 +65,7 @@ tests:
     integration_platforms:
       - nrf54h20dk/nrf54h20/cpuapp
     extra_args:
+      - mbox_CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y
       - SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad.conf
     sysbuild: true
     harness: console

samples/drivers/watchdog/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay

@@ -1,8 +0,0 @@
-/*
- * Copyright 2025 Nordic Semiconductor ASA
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&wdt010 {
-	status = "okay";
-};

samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml

@@ -88,7 +88,7 @@ tests:
       - mimxrt685_evk/mimxrt685s/cm33
       - rd_rw612_bga
       - nrf52840dk/nrf52840
-      - nrf54h20dk/nrf54h20/cpuapp/iron
+      - nrf54h20dk/nrf54h20/cpuapp
       - pinnacle_100_dvk
       - mg100
     integration_platforms:

samples/sysbuild/hello_world/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf

@@ -1,4 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y

samples/sysbuild/hello_world/sample.yaml

@@ -25,13 +25,9 @@ tests:
       - nrf54h20dk/nrf54h20/cpuapp
     integration_platforms:
       - nrf54h20dk/nrf54h20/cpuapp
-    extra_args: SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad.conf
+    extra_args:
-
+      - SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad.conf
-  sample.sysbuild.hello_world.nrf54h20dk_cpuapp_cpurad.iron:
+      - hello_world_CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y
-    platform_allow:
-      - nrf54h20dk/nrf54h20/cpuapp/iron
-    extra_args: SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad_iron.conf
-
   sample.sysbuild.hello_world.nrf54h20dk_cpuapp_cpuppr:
     platform_allow:
       - nrf54h20dk/nrf54h20/cpuapp

samples/sysbuild/hello_world/sysbuild/nrf54h20dk_nrf54h20_cpurad_iron.conf

@@ -1 +0,0 @@
-SB_CONFIG_REMOTE_BOARD="nrf54h20dk/nrf54h20/cpurad/iron"

scripts/west_commands/runners/nrf_common.py

@@ -379,7 +379,7 @@ class NrfBinaryRunner(ZephyrBinaryRunner):
                 )
 
             if self.erase:
-                if self.build_conf.get('CONFIG_SOC_NRF54H20_IRON'):
+                if self.family == 'nrf54h':
                     self.exec_op('erase', kind='all')
                 else:
                     self.exec_op('erase', core='Application', kind='all')
@@ -464,8 +464,8 @@ class NrfBinaryRunner(ZephyrBinaryRunner):
         self.logger.debug(f'Erase modes: chip:{erase_arg} ext_mem:'
                           f'{ext_mem_erase_opt}')
 
-        # Temp hack while waiting for NRF54H20_IRON support for Network in nrfutil
+        # Temp hack while waiting for nrfutil Network support for NRF54H20 with IronSide
-        if self.build_conf.get('CONFIG_SOC_NRF54H20_IRON') and core == "Network":
+        if self.family == 'nrf54h' and core == 'Network':
             core = "Application"
 
         self.op_program(self.hex_, erase_arg, ext_mem_erase_opt, defer=True, core=core)

soc/nordic/ironside/Kconfig

@@ -3,7 +3,7 @@
 
 config NRF_IRONSIDE
 	bool
-	depends on SOC_NRF54H20_IRON || SOC_NRF9280_IRON
+	depends on SOC_NRF54H20 || SOC_NRF9280_IRON
 	help
 	  This is selected by drivers interacting with Nordic IronSide firmware.
 
@@ -28,7 +28,7 @@ config NRF_IRONSIDE_CALL_INIT_PRIORITY
 endif # NRF_IRONSIDE_CALL
 
 menu "Nordic IronSide services"
-	depends on SOC_NRF54H20_IRON || SOC_NRF9280_IRON
+	depends on SOC_NRF54H20 || SOC_NRF9280_IRON
 
 config NRF_IRONSIDE_CPUCONF_SERVICE
 	bool "IronSide CPUCONF service"

soc/nordic/nrf54h/Kconfig

@@ -10,6 +10,7 @@ config SOC_SERIES_NRF54HX
 	select SOC_EARLY_INIT_HOOK if ARM
 	select SOC_LATE_INIT_HOOK if SOC_NRF54H20_CPURAD_ENABLE
 	select NRF_PLATFORM_HALTIUM
+	select EXPERIMENTAL if MCUBOOT
 
 config SOC_NRF54H20_CPUAPP_COMMON
 	bool
@@ -88,6 +89,3 @@ config SOC_NRF54H20_CPUFLPR
 
 rsource "bicr/Kconfig"
 rsource "gpd/Kconfig"
-
-config SOC_NRF54H20_IRON
-	select EXPERIMENTAL if MCUBOOT

soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp

@@ -8,9 +8,6 @@ if SOC_NRF54H20_CPUAPP
 config NUM_IRQS
 	default 471
 
-config NRF_REGTOOL_GENERATE_UICR
-	default y
-
 config SHELL_BACKEND_SERIAL
 	default n if NRF_ETR_SHELL
 

soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad

@@ -8,9 +8,6 @@ if SOC_NRF54H20_CPURAD
 config NUM_IRQS
 	default 471
 
-config NRF_REGTOOL_GENERATE_UICR
-	default y
-
 config PM
 	default y
 

soc/nordic/nrf54h/Kconfig.soc

@@ -33,10 +33,5 @@ config SOC_NRF54H20_CPUFLPR
 	help
 	  nRF54H20 CPUFLPR
 
-config SOC_NRF54H20_IRON
-	bool
-	help
-	  Indicates that local domain firmware is compatible with Nordic IronSide SE.
-
 config SOC
 	default "nrf54h20" if SOC_NRF54H20

tests/boards/nrf/nrfs/prj.conf

@@ -19,3 +19,5 @@ CONFIG_LOG=y
 CONFIG_LOG_MODE_IMMEDIATE=n
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
+
+CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y

tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay

@@ -1,6 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "nrf54h20dk_nrf54h20_common.dtsi"

tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf

@@ -1,2 +0,0 @@
-# Disable dcache
-CONFIG_DCACHE=n

tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay

@@ -1,8 +0,0 @@
-/*
- * Copyright 2025 Nordic Semiconductor ASA
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&wdt010 {
-	status = "okay";
-};

tests/subsys/ipc/ipc_sessions/testcase.yaml

@@ -20,6 +20,7 @@ tests:
       - nrf54h20dk/nrf54h20/cpuapp
     extra_args:
       - CONFIG_IPC_TEST_SKIP_CORE_RESET=y
+      - CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y
   sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpuppr:
     platform_allow:
       - nrf54h20dk/nrf54h20/cpuapp