From aab1f68d08886cd27a034e2ccef55345dfc623d2 Mon Sep 17 00:00:00 2001 From: Robert Hancock Date: Fri, 13 Jun 2025 15:09:18 -0600 Subject: [PATCH] drivers: ethernet: phy: vsc8541: Add timeout on SW reset The driver previously could enter an infinite loop if the PHY software reset failed to complete, which could happen due to hardware reset issues or MDIO bus problems. Add a timeout of 1000 iterations so we report an error in this scenario rather than causing a lockup. Signed-off-by: Robert Hancock --- drivers/ethernet/phy/phy_microchip_vsc8541.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/ethernet/phy/phy_microchip_vsc8541.c b/drivers/ethernet/phy/phy_microchip_vsc8541.c index 6d6cdf0fbfb..afe484af3a1 100644 --- a/drivers/ethernet/phy/phy_microchip_vsc8541.c +++ b/drivers/ethernet/phy/phy_microchip_vsc8541.c @@ -134,6 +134,7 @@ static int phy_mc_vsc8541_reset(const struct device *dev) const struct mc_vsc8541_config *cfg = dev->config; int ret; uint16_t reg = 0U; + int count = 0; #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) @@ -197,8 +198,15 @@ static int phy_mc_vsc8541_reset(const struct device *dev) /* wait for phy finished software reset */ do { - phy_mc_vsc8541_read(dev, MII_BMCR, ®); - } while (reg & MII_BMCR_RESET); + ret = phy_mc_vsc8541_read(dev, MII_BMCR, ®); + if (ret < 0) { + return ret; + } + if (count++ > 1000) { + LOG_ERR("phy reset timed out"); + return -ETIMEDOUT; + } + } while ((reg & MII_BMCR_RESET) != 0U); /* configure the RGMII clk delay */ reg = 0x0;