From a9fb2c4dffc8a14fc90719300348d532e126e79a Mon Sep 17 00:00:00 2001
From: Erwan Gouriou <erwan.gouriou@st.com>
Date: Mon, 27 May 2024 16:54:30 +0200
Subject: [PATCH] soc: stm32g4: Enable ART acceleration

Enable instruction and data cache as well as prefetch.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
---
 soc/st/stm32/stm32g4x/soc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/soc/st/stm32/stm32g4x/soc.c b/soc/st/stm32/stm32g4x/soc.c
index c52d93232c3..befbc239f01 100644
--- a/soc/st/stm32/stm32g4x/soc.c
+++ b/soc/st/stm32/stm32g4x/soc.c
@@ -30,6 +30,11 @@
  */
 static int stm32g4_init(void)
 {
+	/* Enable ART Accelerator I/D-cache and prefetch */
+	LL_FLASH_EnableInstCache();
+	LL_FLASH_EnableDataCache();
+	LL_FLASH_EnablePrefetch();
+
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;