From a8b787f4e7b8adc9d94300a4cc02ea8203ee9a0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH] soc: msp432p4xx: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- .../msp432p4xx/startup_system_files/system_msp432p401m.c | 3 ++- .../msp432p4xx/startup_system_files/system_msp432p401r.c | 3 ++- .../msp432p4xx/startup_system_files/system_msp432p4111.c | 3 ++- .../msp432p4xx/startup_system_files/system_msp432p411v.c | 3 ++- .../msp432p4xx/startup_system_files/system_msp432p411y.c | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c index 5f947f8780d..a3a8c409162 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c index 8637028496b..6b430f35766 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c index a745c08bc16..c9c29c5ae54 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c index 9343fdbe109..a212221bd02 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c index e45fa1fff6b..f5faa778966 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode