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soc: andestech: ae350: add ae350/clic configuration

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Add ae350/clic soc, which shares the same peripherials as AE350 PLIC
platform but uses CLIC instead of PLIC, with different IRQ number.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng 2024-07-03 11:23:06 +08:00 committed by Anas Nashif
parent 13e2125402
commit a36f767519
5 changed files with 43 additions and 17 deletions
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2
soc/andestech/ae350/CMakeLists.txt
View File

@ -24,6 +24,6 @@ if(CONFIG_SOC_ANDES_V5_EXECIT)
zephyr_ld_options(-Wl,--mexecit)
endif()
if(CONFIG_SOC_ANDES_AE350)
if(CONFIG_SOC_SERIES_ANDES_AE350)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
endif()

28
soc/andestech/ae350/Kconfig
View File

@ -4,20 +4,28 @@
config SOC_SERIES_ANDES_AE350
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select RISCV_PMP
select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
imply XIP
config SOC_ANDES_AE350
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
select CACHE_MANAGEMENT if DCACHE
select RISCV_PMP
imply XIP
config SOC_ANDES_AE350
select RISCV_HAS_PLIC
config SOC_ANDES_AE350_CLIC
select RISCV_HAS_CLIC
select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
select CLIC_SMCLICCONFIG_EXT
select LEGACY_CLIC_MEMORYMAP_ACCESS
if SOC_SERIES_ANDES_AE350
@ -28,20 +36,14 @@ default RV32I_CPU
config RV32I_CPU
bool "RISCV32 CPU ISA"
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
config RV32E_CPU
bool "RISCV32E CPU ISA"
select RISCV_ISA_RV32E
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
config RV64I_CPU
bool "RISCV64 CPU ISA"
select RISCV_ISA_RV64I
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select 64BIT
endchoice

18
soc/andestech/ae350/Kconfig.defconfig
View File

@ -21,6 +21,8 @@ config RISCV_GENERIC_TOOLCHAIN
config RISCV_SOC_INTERRUPT_INIT
default y
if RISCV_HAS_PLIC
config 2ND_LVL_ISR_TBL_OFFSET
default 12
@ -39,6 +41,22 @@ config NUM_2ND_LEVEL_AGGREGATORS
config NUM_IRQS
default 116
endif # RISCV_HAS_PLIC
if RISCV_HAS_CLIC
config NUM_IRQS
default 48
config RISCV_MCAUSE_EXCEPTION_MASK
default 0xFFF
config ARCH_IRQ_VECTOR_TABLE_ALIGN
default 512 if RISCV_ISA_RV64I
default 256
endif # RISCV_HAS_CLIC
choice CACHE_TYPE
default EXTERNAL_CACHE
endchoice

4
soc/andestech/ae350/Kconfig.defconfig.ae350
View File

@ -1,7 +1,7 @@
# Copyright (c) 2021 Andes Technology Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_ANDES_AE350
if SOC_ANDES_AE350 || SOC_ANDES_AE350_CLIC
config SYS_CLOCK_TICKS_PER_SEC
default 100 if (!ICACHE || XIP)
@ -22,4 +22,4 @@ config MP_MAX_NUM_CPUS
default 1
range 1 8
endif # SOC_ANDES_AE350
endif # SOC_ANDES_AE350 || SOC_ANDES_AE350_CLIC

8
soc/andestech/ae350/Kconfig.soc
View File

@ -13,8 +13,14 @@ config SOC_ANDES_AE350
help
Andes AE350 SoC implementation"
config SOC_ANDES_AE350_CLIC
bool
select SOC_SERIES_ANDES_AE350
help
Andes AE350 CLIC SoC implementation"
config SOC_SERIES
default "ae350" if SOC_SERIES_ANDES_AE350
config SOC
default "ae350" if SOC_ANDES_AE350
default "ae350" if SOC_ANDES_AE350 || SOC_ANDES_AE350_CLIC