drivers/pcie: Add support for MSI-X
It's disabled by default. When enabled, and if the device exposes both MSI and MSI-X capabilities: MSI-X will be selected and MSI disabled on the device. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Anas Nashif
parent
bfbe9b6df5
commit
a2491b321e
@ -18,9 +18,10 @@ config PCIE_MSI
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runtime) to use them. This is typically required for PCIe devices
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to generate interrupts at all.
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if PCIE_MSI
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config PCIE_MSI_MULTI_VECTOR
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bool "Enable MSI multi-vector support"
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depends on PCIE_MSI
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help
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MSI can support up to 32 different messages. This will enable the
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support of such capability so each message can get a vector
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@ -29,6 +30,16 @@ config PCIE_MSI_MULTI_VECTOR
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the vectors cannot be managed by the hardware or if none of the
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peripheral require this.
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config PCIE_MSI_X
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bool "Enable MSI-X support"
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help
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If one or more device support MSI-X, you'll need to enable this.
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If a device exposes support for both MSI-X and MSI, MSI-X will be
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used and MSI disabled on that device. Enable PCIE_MSI_MULTI_VECTOR
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if you want to support multi-vector on MSI-X as well.
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endif # PCIE_MSI
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config PCIE_SHELL
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bool "Enable PCIe/new PCI Shell"
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default y
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@ -36,27 +36,118 @@ __weak bool arch_pcie_msi_vector_connect(msi_vector_t *vector,
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return false;
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}
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#ifdef CONFIG_PCIE_MSI_X
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static uint32_t get_msix_table_size(pcie_bdf_t bdf,
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uint32_t base)
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{
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uint32_t mcr;
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mcr = pcie_conf_read(bdf, base + PCIE_MSIX_MCR);
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return ((mcr & PCIE_MSIX_MCR_TSIZE) >> PCIE_MSIX_MCR_TSIZE_SHIFT) + 1;
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}
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static bool map_msix_table_entries(pcie_bdf_t bdf,
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uint32_t base,
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msi_vector_t *vectors,
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uint8_t n_vector)
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{
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uint32_t table_offset;
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uint8_t table_bir;
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struct pcie_mbar bar;
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uintptr_t mapped_table;
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int i;
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table_offset = pcie_conf_read(bdf, base + PCIE_MSIX_TR);
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table_bir = table_offset & PCIE_MSIX_TR_BIR;
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table_offset &= PCIE_MSIX_TR_OFFSET;
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if (!pcie_get_mbar(bdf, table_bir, &bar)) {
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return false;
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}
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z_mem_map((uint8_t **)&mapped_table,
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bar.phys_addr + table_offset,
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bar.size, K_MEM_PERM_RW);
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for (i = 0; i < n_vector; i++) {
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vectors[i].msix_vector = (struct msix_vector *)
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(mapped_table + (i * PCIE_MSIR_TABLE_ENTRY_SIZE));
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}
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return true;
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}
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static void set_msix(msi_vector_t *vectors,
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uint8_t n_vector,
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bool msix)
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{
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int i;
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for (i = 0; i < n_vector; i++) {
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vectors[i].msix = msix;
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}
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}
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#else
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#define get_msix_table_size(...) 0
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#define map_msix_table_entries(...) true
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#define set_msix(...)
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#endif /* CONFIG_PCIE_MSI_X */
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static uint32_t get_msi_mmc(pcie_bdf_t bdf,
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uint32_t base)
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{
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uint32_t mcr;
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mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR);
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/* Getting MMC true count: 2^(MMC field) */
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return 1 << ((mcr & PCIE_MSI_MCR_MMC) >> PCIE_MSI_MCR_MMC_SHIFT);
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}
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uint8_t pcie_msi_vectors_allocate(pcie_bdf_t bdf,
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unsigned int priority,
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msi_vector_t *vectors,
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uint8_t n_vector)
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{
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bool msi = true;
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uint32_t base;
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uint32_t mcr;
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uint8_t mmc;
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uint32_t req_vectors;
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base = pcie_get_cap(bdf, PCIE_MSI_CAP_ID);
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if (base == 0U) {
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return 0;
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if (IS_ENABLED(CONFIG_PCIE_MSI_X)) {
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uint32_t base_msix;
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base_msix = pcie_get_cap(bdf, PCIE_MSIX_CAP_ID);
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if (base_msix != 0U) {
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base = base_msix;
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}
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msi = false;
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base = base_msix;
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}
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mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR);
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mmc = (uint8_t)((mcr & PCIE_MSI_MCR_MMC) >> PCIE_MSI_MCR_MMC_SHIFT);
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/* Getting MMC true count: 2^(MMC field) */
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mmc = 1 << mmc;
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if (IS_ENABLED(CONFIG_PCIE_MSI_X)) {
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set_msix(vectors, n_vector, !msi);
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if (n_vector > mmc) {
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n_vector = mmc;
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if (!msi) {
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req_vectors = get_msix_table_size(bdf, base);
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if (!map_msix_table_entries(bdf, base,
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vectors, n_vector)) {
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return 0;
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}
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}
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}
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if (msi) {
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req_vectors = get_msi_mmc(bdf, base);
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}
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if (n_vector > req_vectors) {
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n_vector = req_vectors;
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}
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return arch_pcie_msi_vectors_allocate(priority, vectors, n_vector);
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@ -71,6 +162,16 @@ bool pcie_msi_vector_connect(pcie_bdf_t bdf,
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uint32_t base;
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base = pcie_get_cap(bdf, PCIE_MSI_CAP_ID);
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if (IS_ENABLED(CONFIG_PCIE_MSI_X)) {
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uint32_t base_msix;
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base_msix = pcie_get_cap(bdf, PCIE_MSIX_CAP_ID);
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if (base_msix != 0U) {
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base = base_msix;
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}
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}
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if (base == 0U) {
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return false;
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}
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@ -82,22 +183,59 @@ bool pcie_msi_vector_connect(pcie_bdf_t bdf,
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#endif /* CONFIG_PCIE_MSI_MULTI_VECTOR */
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bool pcie_msi_enable(pcie_bdf_t bdf,
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msi_vector_t *vectors,
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uint8_t n_vector)
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#ifdef CONFIG_PCIE_MSI_X
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static void enable_msix(pcie_bdf_t bdf,
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msi_vector_t *vectors,
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uint8_t n_vector,
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uint32_t base)
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{
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unsigned int irq;
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uint32_t mcr;
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int i;
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irq = pcie_get_irq(bdf);
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for (i = 0; i < n_vector; i++) {
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uint32_t map = pcie_msi_map(irq, &vectors[i]);
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uint32_t mdr = pcie_msi_mdr(irq, &vectors[i]);
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vectors[i].msix_vector->msg_addr = map;
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vectors[i].msix_vector->msg_up_addr = 0;
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vectors[i].msix_vector->msg_data = mdr;
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vectors[i].msix_vector->vector_ctrl = 0;
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}
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mcr = pcie_conf_read(bdf, base + PCIE_MSIX_MCR);
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mcr |= PCIE_MSIX_MCR_EN;
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pcie_conf_write(bdf, base + PCIE_MSIX_MCR, mcr);
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}
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#else
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#define enable_msix(...)
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#endif /* CONFIG_PCIE_MSI_X */
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static void disable_msi(pcie_bdf_t bdf,
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uint32_t base)
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{
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uint32_t mcr;
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mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR);
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mcr &= ~PCIE_MSI_MCR_EN;
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pcie_conf_write(bdf, base + PCIE_MSI_MCR, mcr);
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}
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static void enable_msi(pcie_bdf_t bdf,
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msi_vector_t *vectors,
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uint8_t n_vector,
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uint32_t base)
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{
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unsigned int irq;
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uint32_t base;
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uint32_t mcr;
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uint32_t map;
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uint32_t mdr;
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uint32_t mme;
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base = pcie_get_cap(bdf, PCIE_MSI_CAP_ID);
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if (base == 0U) {
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return false;
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}
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irq = pcie_get_irq(bdf);
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map = pcie_msi_map(irq, vectors);
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@ -121,6 +259,39 @@ bool pcie_msi_enable(pcie_bdf_t bdf,
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mcr |= PCIE_MSI_MCR_EN;
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pcie_conf_write(bdf, base + PCIE_MSI_MCR, mcr);
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}
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bool pcie_msi_enable(pcie_bdf_t bdf,
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msi_vector_t *vectors,
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uint8_t n_vector)
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{
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bool msi = true;
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uint32_t base;
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base = pcie_get_cap(bdf, PCIE_MSI_CAP_ID);
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if (IS_ENABLED(CONFIG_PCIE_MSI_X)) {
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uint32_t base_msix;
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base_msix = pcie_get_cap(bdf, PCIE_MSIX_CAP_ID);
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if ((base_msix != 0U) && (base != 0U)) {
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disable_msi(bdf, base);
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}
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msi = false;
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base = base_msix;
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}
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if (base == 0U) {
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return false;
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}
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if (!msi && IS_ENABLED(CONFIG_PCIE_MSI_X)) {
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enable_msix(bdf, vectors, n_vector, base);
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} else {
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enable_msi(bdf, vectors, n_vector, base);
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}
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pcie_set_cmd(bdf, PCIE_CONF_CMDSTAT_MASTER, true);
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return true;
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@ -17,9 +17,20 @@
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extern "C" {
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#endif
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struct msix_vector {
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uint32_t msg_addr;
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uint32_t msg_up_addr;
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uint32_t msg_data;
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uint32_t vector_ctrl;
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};
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struct msi_vector {
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pcie_bdf_t bdf;
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arch_msi_vector_t arch;
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#ifdef CONFIG_PCIE_MSI_X
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struct msix_vector *msix_vector;
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bool msix;
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#endif /* CONFIG_PCIE_MSI_X */
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};
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typedef struct msi_vector msi_vector_t;
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@ -127,6 +138,28 @@ extern bool pcie_msi_enable(pcie_bdf_t bdf,
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#define PCIE_MSI_MDR_32 2U
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#define PCIE_MSI_MDR_64 3U
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/*
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* As for MSI, he first word of the MSI-X capability is shared
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* with the capability ID and list link. The high 16 bits are the MCR.
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*/
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#define PCIE_MSIX_MCR 0U
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#define PCIE_MSIX_MCR_EN 0x80000000U /* Enable MSI-X */
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#define PCIE_MSIX_MCR_FMASK 0x40000000U /* Function Mask */
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#define PCIE_MSIX_MCR_TSIZE 0x07FF0000U /* Table size mask */
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#define PCIE_MSIX_MCR_TSIZE_SHIFT 16
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#define PCIE_MSIR_TABLE_ENTRY_SIZE 16
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#define PCIE_MSIX_TR 1U
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#define PCIE_MSIX_TR_BIR 0x00000007U /* BIR mask */
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#define PCIE_MSIX_TR_OFFSET 0xFFFFFFF8U /* Offset mask */
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#define PCIE_VTBL_MA 0U /* Msg Address offset */
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#define PCIE_VTBL_MUA 4U /* Msg Upper Address offset */
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#define PCIE_VTBL_MD 8U /* Msg Data offset */
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#define PCIE_VTBL_VCTRL 12U /* Vector control offset */
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#ifdef __cplusplus
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}
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#endif
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