From 9977ce4eb682e026c1719815b439256c36f26542 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Wed, 2 Jul 2025 09:23:40 +0200 Subject: [PATCH] dts: bindings: memc: stm32-fmc: reorder parameters to match code Description of parameters in st,control property didn't match the values used in the code. Modify the description to match with the current driver implementation. Also add a description for reg property to help setting it properly and add corresponding dt-bindings. Signed-off-by: Guillaume Gautier --- .../memory-controllers/st,stm32-fmc-nor-psram.yaml | 8 +++++--- .../dt-bindings/memory-controller/stm32-fmc-nor-psram.h | 6 ++++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/dts/bindings/memory-controllers/st,stm32-fmc-nor-psram.yaml b/dts/bindings/memory-controllers/st,stm32-fmc-nor-psram.yaml index 6b6daf74d85..729e322388c 100644 --- a/dts/bindings/memory-controllers/st,stm32-fmc-nor-psram.yaml +++ b/dts/bindings/memory-controllers/st,stm32-fmc-nor-psram.yaml @@ -87,6 +87,10 @@ child-binding: reg: type: int required: true + description: | + SRAM/NOR Bank value. + This is used to select the bank to which the device is connected. + It should be equal to a value of STM32_FMC_NORSRAM_BANKx. st,control: type: array @@ -102,7 +106,6 @@ child-binding: * MUXEN - Address/data multiplexing enable bit. * MTYP - Memory type. * MWID - Memory data bus width. - * FACCEN - Flash access enable. * BURSTEN - Burst enable bit. * WAITPOL - Wait signal polarity bit. * WAITCFG - Wait timing configuration. @@ -111,11 +114,10 @@ child-binding: * EXTMOD - Extended mode enable. If set, then 'st,timing-ext' shall be provided. * ASYNCWAIT - Wait signal during asynchronous transfers. - * CPSIZE - Cellular RAM (CRAM) 1.5 Page Size. * CBURSTRW - Write burst enable. * CCLKEN - Continuous Clock Enable. * WFDIS - Write FIFO Disable. - * BMAP - FMC bank mapping. + * CPSIZE - Cellular RAM 1.5 Page Size. st,timing: type: array diff --git a/include/zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h b/include/zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h index eb8325c8a8a..129b37b8dee 100644 --- a/include/zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h +++ b/include/zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h @@ -7,6 +7,12 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_ +/* NOR/SRAM Bank */ +#define STM32_FMC_NORSRAM_BANK1 0x00000000UL +#define STM32_FMC_NORSRAM_BANK2 0x00000002UL +#define STM32_FMC_NORSRAM_BANK3 0x00000004UL +#define STM32_FMC_NORSRAM_BANK4 0x00000006UL + /* Data Address Bus Multiplexing */ #define STM32_FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000UL #define STM32_FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002UL