From 8e85600a303d874fb0792327a1ba3148fa3449eb Mon Sep 17 00:00:00 2001
From: Erwan Gouriou <erwan.gouriou@linaro.org>
Date: Fri, 31 Mar 2017 13:08:16 +0200
Subject: [PATCH] drivers: i2c: stm32lx: Add support for I2C_2

Add support for I2C_2 instance on stm32lx driver

Change-Id: Iaa17305dd21f92954274ca522d30d464e0a53b7b
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
---
 drivers/i2c/Kconfig       | 27 ++++++++++++++++++++++++
 drivers/i2c/i2c_stm32lx.c | 44 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 402171d5e9a..7351ea7e709 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -218,6 +218,33 @@ config I2C_1_IRQ_PRI
 	help
 	IRQ priority.
 
+config I2C_2
+	bool "Enable I2C Port 2"
+	depends on I2C
+	default n
+
+config I2C_2_NAME
+	string "Select a name for finding the device"
+	default "I2C_2"
+	depends on I2C_2
+
+config I2C_2_DEFAULT_CFG
+	hex "I2C default configuration"
+	depends on I2C_2
+	default 0x0
+	help
+	Allows the I2C port to be brought up with a default configuration.
+	This is useful to set if other drivers depend upon using the I2C bus
+	before the application has a chance to custom configure the port.
+	Setting this value does not prohibit the application from customizing
+	the values later.  Refer to the I2C datasheet for proper values.
+
+config I2C_2_IRQ_PRI
+	int "Controller interrupt priority"
+	depends on I2C_2 && I2C_0_IRQ_DIRECT
+	help
+	IRQ priority.
+
 config I2C_SS_0
 	bool "Enable I2C_SS_0"
 	depends on I2C_QMSI_SS
diff --git a/drivers/i2c/i2c_stm32lx.c b/drivers/i2c/i2c_stm32lx.c
index f71b6a5097f..2a46a59bfba 100644
--- a/drivers/i2c/i2c_stm32lx.c
+++ b/drivers/i2c/i2c_stm32lx.c
@@ -475,3 +475,47 @@ static void i2c_stm32lx_irq_config_func_1(struct device *dev)
 #endif
 
 #endif /* CONFIG_I2C_1 */
+
+#ifdef CONFIG_I2C_2
+
+#ifdef CONFIG_I2C_STM32LX_INTERRUPT
+static void i2c_stm32lx_irq_config_func_2(struct device *port);
+#endif
+
+static const struct i2c_stm32lx_config i2c_stm32lx_cfg_2 = {
+	.base = (uint8_t *)I2C1_BASE,
+	.pclken = { .bus = STM32_CLOCK_BUS_APB1,
+		    .enr = LL_APB1_GRP1_PERIPH_I2C2 },
+#ifdef CONFIG_I2C_STM32LX_INTERRUPT
+	.irq_config_func = i2c_stm32lx_irq_config_func_2,
+#endif
+};
+
+static struct i2c_stm32lx_data i2c_stm32lx_dev_data_2 = {
+	.dev_config.raw = CONFIG_I2C_2_DEFAULT_CFG,
+};
+
+DEVICE_AND_API_INIT(i2c_stm32lx_2, CONFIG_I2C_2_NAME, &i2c_stm32lx_init,
+		    &i2c_stm32lx_dev_data_2, &i2c_stm32lx_cfg_2,
+		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		    &api_funcs);
+
+#ifdef CONFIG_I2C_STM32LX_INTERRUPT
+static void i2c_stm32lx_irq_config_func_2(struct device *dev)
+{
+#ifdef CONFIG_SOC_SERIES_STM32L4X
+#define PORT_2_EV_IRQ STM32L4_IRQ_I2C2_EV
+#define PORT_2_ER_IRQ STM32L4_IRQ_I2C2_ER
+#endif
+
+	IRQ_CONNECT(PORT_2_EV_IRQ, CONFIG_I2C_2_IRQ_PRI,
+		i2c_stm32lx_ev_isr, DEVICE_GET(i2c_stm32lx_2), 0);
+	irq_enable(PORT_2_EV_IRQ);
+
+	IRQ_CONNECT(PORT_2_ER_IRQ, CONFIG_I2C_2_IRQ_PRI,
+		i2c_stm32lx_er_isr, DEVICE_GET(i2c_stm32lx_2), 0);
+	irq_enable(PORT_2_ER_IRQ);
+}
+#endif
+
+#endif /* CONFIG_I2C_2 */