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boards: nordic: nrf54l20pdk: Remove obsolete board

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Board nrf54l20pdk was renamed to nrf54lm20dk.
Remove obsolete board definition.

Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
This commit is contained in:
Sebastian Głąb 2025-07-22 09:52:19 +02:00 committed by Fabio Baltieri
parent 90717047e0
commit 878ddbe2f6
29 changed files with 8 additions and 1730 deletions
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15
boards/nordic/nrf54l20pdk/Kconfig.defconfig
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@ -1,15 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if BOARD_NRF54L20PDK_NRF54L20_CPUAPP
config HW_STACK_PROTECTION
default ARCH_HAS_STACK_PROTECTION
config ROM_START_OFFSET
default 0x800 if BOOTLOADER_MCUBOOT
config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE
default y
endif # BOARD_NRF54L20PDK_NRF54L20_CPUAPP

6
boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk
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@ -1,6 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config BOARD_NRF54L20PDK
select SOC_NRF54L20_ENGA_CPUAPP if BOARD_NRF54L20PDK_NRF54L20_CPUAPP
select SOC_NRF54L20_ENGA_CPUFLPR if BOARD_NRF54L20PDK_NRF54L20_CPUFLPR

11
boards/nordic/nrf54l20pdk/board.cmake
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@ -1,11 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUAPP)
board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
elseif(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUFLPR)
board_runner_args(jlink "--speed=4000")
endif()
include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

6
boards/nordic/nrf54l20pdk/board.yml
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@ -1,6 +0,0 @@
board:
name: nrf54l20pdk
full_name: nRF54L20 PDK
vendor: nordic
socs:
- name: nrf54l20

77
boards/nordic/nrf54l20pdk/doc/index.rst
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@ -1,77 +0,0 @@
.. zephyr:board:: nrf54l20pdk
Overview
********
.. note::
All software for the nRF54L20 SoC is experimental and hardware availability
is restricted to the participants in the limited sampling program.
The nRF54L20 Preview Development Kit hardware provides
support for the Nordic Semiconductor nRF54L20 Arm Cortex-M33 CPU and
the following devices:
* CLOCK
* RRAM
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`GRTC (Global real-time counter)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
Hardware
********
nRF54L20 PDK has two crystal oscillators:
* High-frequency 32 MHz crystal oscillator (HFXO)
* Low-frequency 32.768 kHz crystal oscillator (LFXO)
The crystal oscillators can be configured to use either
internal or external capacitors.
Supported Features
==================
.. zephyr:board-supported-hw::
Programming and Debugging
*************************
.. zephyr:board-supported-runners::
Applications for the ``nrf54l20pdk/nrf54l20/cpuapp`` board target can be
built, flashed, and debugged in the usual way. See
:ref:`build_an_application` and :ref:`application_run` for more details on
building and running.
Applications for the ``nrf54l20pdk/nrf54l20/cpuflpr`` board target need
to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
Enter the following command to compile ``hello_world`` for the FLPR core::
west build -p -b nrf54l20pdk/nrf54l20/cpuflpr --sysbuild
Flashing
========
As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
application.
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`.
To build and program the sample to the nRF54L20 PDK, complete the following steps:
First, connect the nRF54L20 PDK to you computer using the IMCU USB port on the PDK.
Next, build the sample by running the following command:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf54l20pdk/nrf54l20/cpuapp
:goals: build flash
Testing the LEDs and buttons in the nRF54L20 PDK
************************************************
Test the nRF54L20 PDK with a :zephyr:code-sample:`blinky` sample.

131
boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi
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@ -1,131 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* This file is common to the secure and non-secure domain */
#include <nordic/nrf54l20_enga_cpuapp.dtsi>
#include "nrf54l20pdk_nrf54l20-common.dtsi"
/ {
chosen {
zephyr,console = &uart20;
zephyr,shell-uart = &uart20;
zephyr,uart-mcumgr = &uart20;
zephyr,bt-mon-uart = &uart20;
zephyr,bt-c2h-uart = &uart20;
zephyr,flash-controller = &rram_controller;
zephyr,flash = &cpuapp_rram;
zephyr,bt-hci = &bt_hci_controller;
zephyr,ieee802154 = &ieee802154;
};
};
&cpuapp_sram {
status = "okay";
};
&lfxo {
load-capacitors = "internal";
load-capacitance-femtofarad = <15500>;
};
&hfxo {
load-capacitors = "internal";
load-capacitance-femtofarad = <15000>;
};
&grtc {
owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
child-owned-channels = <3 4 7 8 9 10 11>;
status = "okay";
};
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x10000 DT_SIZE_K(449)>;
};
slot0_ns_partition: partition@80400 {
label = "image-0-nonsecure";
reg = <0x80400 DT_SIZE_K(449)>;
};
slot1_partition: partition@f0800 {
label = "image-1";
reg = <0xf0800 DT_SIZE_K(449)>;
};
slot1_ns_partition: partition@160c00 {
label = "image-1-nonsecure";
reg = <0x160c00 DT_SIZE_K(449)>;
};
storage_partition: partition@1d1000 {
label = "storage";
reg = <0x1d1000 DT_SIZE_K(36)>;
};
};
};
&uart20 {
status = "okay";
};
&nfct {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpiote20 {
status = "okay";
};
&gpiote30 {
status = "okay";
};
&radio {
status = "okay";
};
&temp {
status = "okay";
};
&clock {
status = "okay";
};
&bt_hci_controller {
status = "okay";
};
&ieee802154 {
status = "okay";
};

114
boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi
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@ -1,114 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf54l20pdk_nrf54l20-pinctrl.dtsi"
/ {
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
label = "Green LED 1";
};
led2: led_2 {
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
label = "Green LED 2";
};
led3: led_3 {
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
label = "Green LED 3";
};
};
pwmleds {
compatible = "pwm-leds";
/*
* PWM signal can be exposed on GPIO pin only within same domain.
* There is only one domain which contains both PWM and GPIO:
* PWM20/21/22 and GPIO Port P1/P3.
* Only LEDs connected to P1/P3 can work with PWM, for example LED1.
*/
pwm_led1: pwm_led_1 {
pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 0";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_1>;
};
button2: button_2 {
gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_2>;
};
button3: button_3 {
gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 3";
zephyr,code = <INPUT_KEY_3>;
};
};
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
pwm-led0 = &pwm_led1;
sw0 = &button0;
sw1 = &button1;
sw2 = &button2;
sw3 = &button3;
watchdog0 = &wdt31;
};
};
&uart20 {
current-speed = <115200>;
pinctrl-0 = <&uart20_default>;
pinctrl-1 = <&uart20_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm20 {
status = "okay";
pinctrl-0 = <&pwm20_default>;
pinctrl-1 = <&pwm20_sleep>;
pinctrl-names = "default", "sleep";
};
&uart30 {
current-speed = <115200>;
pinctrl-0 = <&uart30_default>;
pinctrl-1 = <&uart30_sleep>;
pinctrl-names = "default", "sleep";
};
&hfpll {
/* For now use 64 MHz clock for CPU and fast peripherals. */
clock-frequency = <DT_FREQ_M(64)>;
};

61
boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi
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@ -1,61 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
/omit-if-no-ref/ uart20_default: uart20_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 4)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 5)>;
bias-pull-up;
};
};
/omit-if-no-ref/ uart20_sleep: uart20_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 4)>,
<NRF_PSEL(UART_RX, 1, 5)>;
low-power-enable;
};
};
/omit-if-no-ref/ pwm20_default: pwm20_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 7)>;
};
};
/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 7)>;
low-power-enable;
};
};
/omit-if-no-ref/ uart30_default: uart30_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 0)>,
<NRF_PSEL(UART_RTS, 0, 2)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 1)>,
<NRF_PSEL(UART_CTS, 0, 3)>;
bias-pull-up;
};
};
/omit-if-no-ref/ uart30_sleep: uart30_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 0)>,
<NRF_PSEL(UART_RX, 0, 1)>,
<NRF_PSEL(UART_RTS, 0, 2)>,
<NRF_PSEL(UART_CTS, 0, 3)>;
low-power-enable;
};
};
};

19
boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts
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@ -1,19 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "nrf54l20_cpuapp_common.dtsi"
/ {
compatible = "nordic,nrf54l20pdk_nrf54l20-cpuapp";
model = "Nordic nRF54L20 PDK nRF54L20 Application MCU";
chosen {
zephyr,code-partition = &slot0_partition;
zephyr,sram = &cpuapp_sram;
};
};

23
boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml
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@ -1,23 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54l20pdk/nrf54l20/cpuapp
name: nRF54L20-PDK-nRF54L20-Application
type: mcu
arch: arm
toolchain:
- gnuarmemb
- zephyr
sysbuild: true
ram: 512
flash: 449
supported:
- adc
- counter
- dmic
- gpio
- i2c
- i2s
- pwm
- spi
- watchdog

15
boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig
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@ -1,15 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable MPU
CONFIG_ARM_MPU=y

68
boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts
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@ -1,68 +0,0 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54l20_enga_cpuflpr.dtsi>
#include "nrf54l20pdk_nrf54l20-common.dtsi"
/ {
model = "Nordic nRF54L20 PDK nRF54L20 FLPR MCU";
compatible = "nordic,nrf54l20pdk_nrf54l20-cpuflpr";
chosen {
zephyr,console = &uart30;
zephyr,shell-uart = &uart30;
zephyr,code-partition = &cpuflpr_code_partition;
zephyr,flash = &cpuflpr_rram;
zephyr,sram = &cpuflpr_sram;
};
};
&cpuflpr_sram {
status = "okay";
};
&cpuflpr_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: partition@0 {
label = "image-0";
reg = <0x0 DT_SIZE_K(64)>;
};
};
};
&grtc {
owned-channels = <3 4>;
status = "okay";
};
&uart30 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpiote20 {
status = "okay";
};
&gpiote30 {
status = "okay";
};

16
boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml
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@ -1,16 +0,0 @@
# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54l20pdk/nrf54l20/cpuflpr
name: nRF54L20-PDK-nRF54L20-Fast-Lightweight-Peripheral-Processor
type: mcu
arch: riscv
toolchain:
- zephyr
sysbuild: true
ram: 64
flash: 64
supported:
- counter
- gpio
- watchdog

17
boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig
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@ -1,17 +0,0 @@
# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
CONFIG_USE_DT_CODE_PARTITION=y
# Execute from SRAM
CONFIG_XIP=n

1
doc/_scripts/redirects.py
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@ -16,6 +16,7 @@ REDIRECTS = [
# zephyr-keep-sorted-start
('application/index', 'develop/application/index'),
('boards/arduino/uno_r4_minima/doc/index', 'boards/arduino/uno_r4/doc/index'),
('boards/nordic/nrf54l20pdk/doc/index', 'boards/nordic/nrf54lm20dk/doc/index'),
('boards/phytec/mimx8mm_phyboard_polis/doc/index', 'boards/phytec/phyboard_polis/doc/index'),
('boards/phytec/mimx8mp_phyboard_pollux/doc/index', 'boards/phytec/phyboard_pollux/doc/index'),
('boards/rak/index', 'boards/rakwireless/index'),

2
doc/releases/release-notes-4.0.rst
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@ -290,7 +290,7 @@ Boards & SoC Support
* :zephyr:board:`Gardena Smart Garden Radio Module <sgrm>` (``sgrm``)
* :zephyr:board:`mikroe STM32 M4 Clicker <mikroe_stm32_m4_clicker>` (``mikroe_stm32_m4_clicker``)
* :zephyr:board:`Nordic Semiconductor nRF54L15 DK <nrf54l15dk>` (``nrf54l15dk``)
* :zephyr:board:`Nordic Semiconductor nRF54L20 PDK <nrf54l20pdk>` (``nrf54l20pdk``)
* Nordic Semiconductor nRF54L20 PDK (``nrf54l20pdk``)
* :zephyr:board:`Nordic Semiconductor nRF7002 DK <nrf7002dk>` (``nrf7002dk``)
* :zephyr:board:`Nuvoton NPCM400_EVB <npcm400_evb>` (``npcm400_evb``)
* :zephyr:board:`NXP FRDM-MCXA156 <frdm_mcxa156>` (``frdm_mcxa156``)

3
doc/releases/release-notes-4.3.rst
View File

@ -103,3 +103,6 @@ Other notable changes
..
Any more descriptive subsystem or driver changes. Do you really want to write
a paragraph or is it enough to link to the api/driver/Kconfig/board page above?
* Removed support for Nordic Semiconductor nRF54L20 PDK (``nrf54l20pdk``) since it is
replaced with :zephyr:board:`nrf54lm20dk` (``nrf54lm20dk``).

116
dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi
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@ -1,116 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nordic/nrf54l20.dtsi>
cpu: &cpuapp {};
systick: &cpuapp_systick {};
nvic: &cpuapp_nvic {};
/delete-node/ &cpuflpr;
/delete-node/ &cpuflpr_rram;
/delete-node/ &cpuflpr_sram;
/delete-node/ &cpuflpr_clic;
/ {
soc {
compatible = "simple-bus";
interrupt-parent = <&cpuapp_nvic>;
ranges;
};
psa_rng: psa-rng {
compatible = "zephyr,psa-crypto-rng";
status = "disabled";
};
};
&cpuflpr_vpr {
cpuapp_vevif_rx: mailbox@1 {
compatible = "nordic,nrf-vevif-event-rx";
reg = <0x0 0x1000>;
status = "disabled";
interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>;
#mbox-cells = <1>;
nordic,events = <1>;
nordic,events-mask = <0x00100000>;
};
cpuapp_vevif_tx: mailbox@0 {
compatible = "nordic,nrf-vevif-task-tx";
reg = <0x0 0x1000>;
#mbox-cells = <1>;
nordic,tasks = <7>;
nordic,tasks-mask = <0x007f0000>;
status = "disabled";
};
};
&cpuapp_ppb {
compatible = "simple-bus";
ranges;
};
&grtc {
interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>,
<229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */
};
&gpiote20 {
interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>;
};
&gpiote30 {
interrupts = <269 NRF_DEFAULT_IRQ_PRIORITY>;
};
&dppic00 {
status = "okay";
};
&dppic10 {
status = "okay";
};
&dppic20 {
status = "okay";
};
&dppic30 {
status = "okay";
};
&ppib00 {
status = "okay";
};
&ppib01 {
status = "okay";
};
&ppib10 {
status = "okay";
};
&ppib11 {
status = "okay";
};
&ppib20 {
status = "okay";
};
&ppib21 {
status = "okay";
};
&ppib22 {
status = "okay";
};
&ppib30 {
status = "okay";
};

67
dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi
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@ -1,67 +0,0 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nordic/nrf54l20.dtsi>
cpu: &cpuflpr {};
clic: &cpuflpr_clic {};
/delete-node/ &cpuapp;
/delete-node/ &cpuapp_rram;
/delete-node/ &cpuapp_ppb;
/delete-node/ &cpuapp_sram;
/ {
soc {
compatible = "simple-bus";
interrupt-parent = <&cpuflpr_clic>;
ranges;
};
};
&cpuflpr {
cpuflpr_vevif_rx: mailbox {
compatible = "nordic,nrf-vevif-task-rx";
status = "disabled";
interrupt-parent = <&cpuflpr_clic>;
interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>,
<17 NRF_DEFAULT_IRQ_PRIORITY>,
<18 NRF_DEFAULT_IRQ_PRIORITY>,
<19 NRF_DEFAULT_IRQ_PRIORITY>,
<20 NRF_DEFAULT_IRQ_PRIORITY>,
<21 NRF_DEFAULT_IRQ_PRIORITY>,
<22 NRF_DEFAULT_IRQ_PRIORITY>;
#mbox-cells = <1>;
nordic,tasks = <7>;
nordic,tasks-mask = <0x007f0000>;
};
};
&cpuflpr_vpr {
cpuflpr_vevif_tx: mailbox {
compatible = "nordic,nrf-vevif-event-tx";
#mbox-cells = <1>;
nordic,events = <1>;
nordic,events-mask = <0x00100000>;
status = "disabled";
};
};
&cpuflpr_clic {
status = "okay";
};
&grtc {
interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
};
&gpiote20 {
interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
};
&gpiote30 {
interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
};

851
dts/vendor/nordic/nrf54l20.dtsi vendored
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@ -1,851 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/delete-node/ &sw_pwm;
/* Domain IDs. Can be used to specify channel links in IPCT nodes. */
#define NRF_DOMAIN_ID_APPLICATION 0
#define NRF_DOMAIN_ID_FLPR 1
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpuapp: cpu@0 {
compatible = "arm,cortex-m33f";
reg = <0>;
device_type = "cpu";
clocks = <&hfpll>;
#address-cells = <1>;
#size-cells = <1>;
itm: itm@e0000000 {
compatible = "arm,armv8m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <DT_FREQ_M(128)>;
};
};
cpuflpr: cpu@1 {
compatible = "nordic,vpr";
reg = <1>;
device_type = "cpu";
riscv,isa = "rv32emc";
nordic,bus-width = <64>;
};
};
clocks {
pclk: pclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <DT_FREQ_M(16)>;
};
pclk32m: pclk32m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <DT_FREQ_M(32)>;
};
lfxo: lfxo {
compatible = "nordic,nrf54l-lfxo";
#clock-cells = <0>;
clock-frequency = <32768>;
};
hfxo: hfxo {
compatible = "nordic,nrf54l-hfxo";
#clock-cells = <0>;
clock-frequency = <DT_FREQ_M(32)>;
startup-time-us = <1650>;
};
hfpll: hfpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <DT_FREQ_M(128)>;
};
aclk: aclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <DT_FREQ_M(24)>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ficr: ficr@ffc000 {
compatible = "nordic,nrf-ficr";
reg = <0xffc000 0x1000>;
#nordic,ficr-cells = <1>;
};
uicr: uicr@ffd000 {
compatible = "nordic,nrf-uicr";
reg = <0xffd000 0x1000>;
};
cpuapp_sram: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(447)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20000000 0x6fc00>;
};
cpuflpr_sram: memory@2006fc00 {
compatible = "mmio-sram";
reg = <0x2006fc00 DT_SIZE_K(64)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2006fc00 0x10000>;
};
global_peripherals: peripheral@50000000 {
ranges = <0x0 0x50000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
dppic00: dppic@42000 {
compatible = "nordic,nrf-dppic";
reg = <0x42000 0x808>;
status = "disabled";
};
ppib00: ppib@44000 {
compatible = "nordic,nrf-ppib";
reg = <0x44000 0x1000>;
status = "disabled";
};
ppib01: ppib@45000 {
compatible = "nordic,nrf-ppib";
reg = <0x45000 0x1000>;
status = "disabled";
};
cpuflpr_vpr: vpr@4c000 {
compatible = "nordic,nrf-vpr-coprocessor";
reg = <0x4c000 0x1000>;
ranges = <0x0 0x4c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
enable-secure;
cpuflpr_clic: interrupt-controller@f0000000 {
compatible = "nordic,nrf-clic";
reg = <0xf0000000 0x143c>;
interrupt-controller;
#interrupt-cells = <2>;
#address-cells = <1>;
status = "disabled";
};
};
spi00: spi@4d000 {
/*
* This spi node can be either SPIM or SPIS,
* for the user to pick:
* compatible = "nordic,nrf-spim" or
* "nordic,nrf-spis".
*/
compatible = "nordic,nrf-spim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4d000 0x1000>;
interrupts = <77 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(32)>;
easydma-maxcnt-bits = <16>;
rx-delay-supported;
rx-delay = <1>;
status = "disabled";
};
uart00: uart@4d000 {
compatible = "nordic,nrf-uarte";
reg = <0x4d000 0x1000>;
interrupts = <77 NRF_DEFAULT_IRQ_PRIORITY>;
clocks = <&hfpll>;
status = "disabled";
endtx-stoptx-supported;
frame-timeout-supported;
};
gpio2: gpio@50400 {
compatible = "nordic,nrf-gpio";
gpio-controller;
reg = <0x50400 0x300>;
#gpio-cells = <2>;
ngpios = <11>;
status = "disabled";
port = <2>;
};
timer00: timer@55000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0x55000 0x1000>;
cc-num = <6>;
max-bit-width = <32>;
interrupts = <85 NRF_DEFAULT_IRQ_PRIORITY>;
clocks = <&hfpll>;
prescaler = <0>;
};
dppic10: dppic@82000 {
compatible = "nordic,nrf-dppic";
reg = <0x82000 0x808>;
status = "disabled";
};
ppib10: ppib@83000 {
compatible = "nordic,nrf-ppib";
reg = <0x83000 0x1000>;
status = "disabled";
};
ppib11: ppib@84000 {
compatible = "nordic,nrf-ppib";
reg = <0x84000 0x1000>;
status = "disabled";
};
timer10: timer@85000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0x85000 0x1000>;
cc-num = <8>;
max-bit-width = <32>;
interrupts = <133 NRF_DEFAULT_IRQ_PRIORITY>;
clocks = <&hfxo>;
prescaler = <0>;
};
egu10: egu@87000 {
compatible = "nordic,nrf-egu";
reg = <0x87000 0x1000>;
interrupts = <135 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
radio: radio@8a000 {
compatible = "nordic,nrf-radio";
reg = <0x8a000 0x1000>;
interrupts = <138 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
dfe-supported;
ieee802154-supported;
ble-2mbps-supported;
ble-coded-phy-supported;
cs-supported;
ieee802154: ieee802154 {
compatible = "nordic,nrf-ieee802154";
status = "disabled";
};
/* Note: In the nRF Connect SDK the SoftDevice Controller
* is added and set as the default Bluetooth Controller.
*/
bt_hci_controller: bt_hci_controller {
compatible = "zephyr,bt-hci-ll-sw-split";
status = "disabled";
};
};
dppic20: dppic@c2000 {
compatible = "nordic,nrf-dppic";
reg = <0xc2000 0x808>;
status = "disabled";
};
ppib20: ppib@c3000 {
compatible = "nordic,nrf-ppib";
reg = <0xc3000 0x1000>;
status = "disabled";
};
ppib21: ppib@c4000 {
compatible = "nordic,nrf-ppib";
reg = <0xc4000 0x1000>;
status = "disabled";
};
ppib22: ppib@c5000 {
compatible = "nordic,nrf-ppib";
reg = <0xc5000 0x1000>;
status = "disabled";
};
i2c20: i2c@c6000 {
compatible = "nordic,nrf-twim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc6000 0x1000>;
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <16>;
status = "disabled";
zephyr,pm-device-runtime-auto;
};
spi20: spi@c6000 {
/*
* This spi node can be either SPIM or SPIS,
* for the user to pick:
* compatible = "nordic,nrf-spim" or
* "nordic,nrf-spis".
*/
compatible = "nordic,nrf-spim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc6000 0x1000>;
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
easydma-maxcnt-bits = <16>;
rx-delay-supported;
rx-delay = <1>;
status = "disabled";
};
uart20: uart@c6000 {
compatible = "nordic,nrf-uarte";
reg = <0xc6000 0x1000>;
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
endtx-stoptx-supported;
frame-timeout-supported;
};
i2c21: i2c@c7000 {
compatible = "nordic,nrf-twim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc7000 0x1000>;
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <16>;
status = "disabled";
zephyr,pm-device-runtime-auto;
};
spi21: spi@c7000 {
/*
* This spi node can be either SPIM or SPIS,
* for the user to pick:
* compatible = "nordic,nrf-spim" or
* "nordic,nrf-spis".
*/
compatible = "nordic,nrf-spim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc7000 0x1000>;
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
easydma-maxcnt-bits = <16>;
rx-delay-supported;
rx-delay = <1>;
status = "disabled";
};
uart21: uart@c7000 {
compatible = "nordic,nrf-uarte";
reg = <0xc7000 0x1000>;
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
endtx-stoptx-supported;
frame-timeout-supported;
};
i2c22: i2c@c8000 {
compatible = "nordic,nrf-twim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc8000 0x1000>;
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <16>;
status = "disabled";
zephyr,pm-device-runtime-auto;
};
spi22: spi@c8000 {
/*
* This spi node can be either SPIM or SPIS,
* for the user to pick:
* compatible = "nordic,nrf-spim" or
* "nordic,nrf-spis".
*/
compatible = "nordic,nrf-spim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc8000 0x1000>;
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
easydma-maxcnt-bits = <16>;
rx-delay-supported;
rx-delay = <1>;
status = "disabled";
};
uart22: uart@c8000 {
compatible = "nordic,nrf-uarte";
reg = <0xc8000 0x1000>;
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
endtx-stoptx-supported;
frame-timeout-supported;
};
egu20: egu@c9000 {
compatible = "nordic,nrf-egu";
reg = <0xc9000 0x1000>;
interrupts = <201 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
timer20: timer@ca000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0xca000 0x1000>;
cc-num = <6>;
max-bit-width = <32>;
interrupts = <202 NRF_DEFAULT_IRQ_PRIORITY>;
prescaler = <0>;
};
timer21: timer@cb000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0xcb000 0x1000>;
cc-num = <6>;
max-bit-width = <32>;
interrupts = <203 NRF_DEFAULT_IRQ_PRIORITY>;
prescaler = <0>;
};
timer22: timer@cc000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0xcc000 0x1000>;
cc-num = <6>;
max-bit-width = <32>;
interrupts = <204 NRF_DEFAULT_IRQ_PRIORITY>;
prescaler = <0>;
};
timer23: timer@cd000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0xcd000 0x1000>;
cc-num = <6>;
max-bit-width = <32>;
interrupts = <205 NRF_DEFAULT_IRQ_PRIORITY>;
prescaler = <0>;
};
timer24: timer@ce000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0xce000 0x1000>;
cc-num = <6>;
max-bit-width = <32>;
interrupts = <206 NRF_DEFAULT_IRQ_PRIORITY>;
prescaler = <0>;
};
pdm20: pdm@d0000 {
compatible = "nordic,nrf-pdm";
status = "disabled";
reg = <0xd0000 0x1000>;
interrupts = <208 NRF_DEFAULT_IRQ_PRIORITY>;
};
pdm21: pdm@d1000 {
compatible = "nordic,nrf-pdm";
status = "disabled";
reg = <0xd1000 0x1000>;
interrupts = <209 NRF_DEFAULT_IRQ_PRIORITY>;
};
pwm20: pwm@d2000 {
compatible = "nordic,nrf-pwm";
status = "disabled";
reg = <0xd2000 0x1000>;
interrupts = <210 NRF_DEFAULT_IRQ_PRIORITY>;
#pwm-cells = <3>;
idleout-supported;
};
pwm21: pwm@d3000 {
compatible = "nordic,nrf-pwm";
status = "disabled";
reg = <0xd3000 0x1000>;
interrupts = <211 NRF_DEFAULT_IRQ_PRIORITY>;
#pwm-cells = <3>;
idleout-supported;
};
pwm22: pwm@d4000 {
compatible = "nordic,nrf-pwm";
status = "disabled";
reg = <0xd4000 0x1000>;
interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>;
#pwm-cells = <3>;
idleout-supported;
};
adc: adc@d5000 {
compatible = "nordic,nrf-saadc";
reg = <0xd5000 0x1000>;
interrupts = <213 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
#io-channel-cells = <1>;
zephyr,pm-device-runtime-auto;
};
nfct: nfct@d6000 {
compatible = "nordic,nrf-nfct";
reg = <0xd6000 0x1000>;
interrupts = <214 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
temp: temp@d7000 {
compatible = "nordic,nrf-temp";
reg = <0xd7000 0x1000>;
interrupts = <215 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
gpio1: gpio@d8200 {
compatible = "nordic,nrf-gpio";
gpio-controller;
reg = <0xd8200 0x300>;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
port = <1>;
gpiote-instance = <&gpiote20>;
};
gpiote20: gpiote@da000 {
compatible = "nordic,nrf-gpiote";
reg = <0xda000 0x1000>;
status = "disabled";
instance = <20>;
};
qdec20: qdec@e0000 {
compatible = "nordic,nrf-qdec";
reg = <0xe0000 0x1000>;
interrupts = <224 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
qdec21: qdec@e1000 {
compatible = "nordic,nrf-qdec";
reg = <0xe1000 0x1000>;
interrupts = <225 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
grtc: grtc@e2000 {
compatible = "nordic,nrf-grtc";
reg = <0xe2000 0x1000>;
cc-num = <12>;
clocks = <&lfxo>, <&pclk>;
clock-names = "lfclock", "hfclock";
status = "disabled";
};
tdm: tdm@e8000 {
compatible = "nordic,nrf-tdm";
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe8000 0x1000>;
interrupts = <232 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
clocks = <&pclk32m>;
};
i2c23: i2c@ed000 {
compatible = "nordic,nrf-twim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xed000 0x1000>;
interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <16>;
status = "disabled";
zephyr,pm-device-runtime-auto;
};
spi23: spi@ed000 {
/*
* This spi node can be either SPIM or SPIS,
* for the user to pick:
* compatible = "nordic,nrf-spim" or
* "nordic,nrf-spis".
*/
compatible = "nordic,nrf-spim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xed000 0x1000>;
interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
easydma-maxcnt-bits = <16>;
rx-delay-supported;
rx-delay = <1>;
status = "disabled";
};
uart23: uart@ed000 {
compatible = "nordic,nrf-uarte";
reg = <0xed000 0x1000>;
interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
endtx-stoptx-supported;
frame-timeout-supported;
};
i2c24: i2c@ee000 {
compatible = "nordic,nrf-twim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xee000 0x1000>;
interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <16>;
status = "disabled";
zephyr,pm-device-runtime-auto;
};
spi24: spi@ee000 {
/*
* This spi node can be either SPIM or SPIS,
* for the user to pick:
* compatible = "nordic,nrf-spim" or
* "nordic,nrf-spis".
*/
compatible = "nordic,nrf-spim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xee000 0x1000>;
interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
easydma-maxcnt-bits = <16>;
rx-delay-supported;
rx-delay = <1>;
status = "disabled";
};
uart24: uart@ee000 {
compatible = "nordic,nrf-uarte";
reg = <0xee000 0x1000>;
interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
endtx-stoptx-supported;
frame-timeout-supported;
};
dppic30: dppic@102000 {
compatible = "nordic,nrf-dppic";
reg = <0x102000 0x808>;
status = "disabled";
};
ppib30: ppib@103000 {
compatible = "nordic,nrf-ppib";
reg = <0x103000 0x1000>;
status = "disabled";
};
i2c30: i2c@104000 {
compatible = "nordic,nrf-twim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x104000 0x1000>;
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <16>;
status = "disabled";
zephyr,pm-device-runtime-auto;
};
spi30: spi@104000 {
/*
* This spi node can be either SPIM or SPIS,
* for the user to pick:
* compatible = "nordic,nrf-spim" or
* "nordic,nrf-spis".
*/
compatible = "nordic,nrf-spim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x104000 0x1000>;
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
easydma-maxcnt-bits = <16>;
rx-delay-supported;
rx-delay = <1>;
status = "disabled";
};
uart30: uart@104000 {
compatible = "nordic,nrf-uarte";
reg = <0x104000 0x1000>;
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
endtx-stoptx-supported;
frame-timeout-supported;
};
comp: comparator@106000 {
/*
* Use compatible "nordic,nrf-comp" to configure as COMP
* Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP
*/
compatible = "nordic,nrf-comp";
reg = <0x106000 0x1000>;
status = "disabled";
interrupts = <262 NRF_DEFAULT_IRQ_PRIORITY>;
};
wdt30: watchdog@108000 {
compatible = "nordic,nrf-wdt";
reg = <0x108000 0x620>;
interrupts = <264 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
wdt31: watchdog@109000 {
compatible = "nordic,nrf-wdt";
reg = <0x109000 0x620>;
interrupts = <265 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
gpio0: gpio@10a000 {
compatible = "nordic,nrf-gpio";
gpio-controller;
reg = <0x10a000 0x300>;
#gpio-cells = <2>;
ngpios = <5>;
status = "disabled";
port = <0>;
gpiote-instance = <&gpiote30>;
};
gpiote30: gpiote@10c000 {
compatible = "nordic,nrf-gpiote";
reg = <0x10c000 0x1000>;
status = "disabled";
instance = <30>;
};
clock: clock@10e000 {
compatible = "nordic,nrf-clock";
reg = <0x10e000 0x1000>;
interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
power: power@10e000 {
compatible = "nordic,nrf-power";
reg = <0x10e000 0x1000>;
ranges = <0x0 0x10e000 0x1000>;
interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
gpregret1: gpregret1@500 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "nordic,nrf-gpregret";
reg = <0x500 0x1>;
status = "disabled";
};
gpregret2: gpregret2@504 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "nordic,nrf-gpregret";
reg = <0x504 0x1>;
status = "disabled";
};
};
regulators: regulator@120000 {
compatible = "nordic,nrf54l-regulators";
reg = <0x120000 0x1000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
vregmain: regulator@120600 {
compatible = "nordic,nrf5x-regulator";
reg = <0x120600 0x1>;
status = "disabled";
regulator-name = "VREGMAIN";
regulator-initial-mode = <NRF5X_REG_MODE_LDO>;
};
};
};
rram_controller: rram-controller@5004e000 {
compatible = "nordic,rram-controller";
reg = <0x5004e000 0x1000>;
interrupts = <78 NRF_DEFAULT_IRQ_PRIORITY>;
#address-cells = <1>;
#size-cells = <1>;
cpuapp_rram: rram@0 {
compatible = "soc-nv-flash";
reg = <0x0 DT_SIZE_K(1972)>;
erase-block-size = <4096>;
write-block-size = <16>;
};
cpuflpr_rram: rram@1ed000 {
compatible = "soc-nv-flash";
reg = <0x1ed000 DT_SIZE_K(64)>;
erase-block-size = <4096>;
write-block-size = <16>;
};
};
cpuapp_ppb: cpuapp-ppb-bus {
#address-cells = <1>;
#size-cells = <1>;
cpuapp_nvic: interrupt-controller@e000e100 {
#address-cells = <1>;
compatible = "arm,v8m-nvic";
reg = <0xe000e100 0xc00>;
arm,num-irq-priority-bits = <3>;
interrupt-controller;
#interrupt-cells = <2>;
};
cpuapp_systick: timer@e000e010 {
compatible = "arm,armv8m-systick";
reg = <0xe000e010 0x10>;
status = "disabled";
};
};
};
};

9
modules/hal_nordic/nrfx/CMakeLists.txt
View File

@ -60,9 +60,6 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_CPUAPP NRF_APPLICATION)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR NRF_FLPR)
zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54L15 NRF54L15_XXAA)
zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54L15_CPUAPP NRF_APPLICATION)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L20_ENGA NRF54LM20A_ENGA_XXAA)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUAPP NRF_APPLICATION)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUFLPR NRF_FLPR)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA NRF54LM20A_ENGA_XXAA)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP NRF_APPLICATION)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR NRF_FLPR)
@ -204,9 +201,9 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_DISABLE_FICR_TRIMCNF NRF_DIS
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE NRF_SKIP_GLITCHDETECTOR_DISABLE)
zephyr_compile_definitions_ifndef(CONFIG_SOC_NRF54L_ANOMALY_56_WORKAROUND NRF54L_CONFIGURATION_56_ENABLE=0)
# Inject code to skip TAMPC setup for nRF54L20 and nRF54L09. It is not supported for now.
# Inject code to skip TAMPC setup for nRF54LM20A and nRF54L09. It is not supported for now.
# It needs to be removed when support is provided.
if(CONFIG_SOC_NRF54L20_ENGA_CPUAPP OR CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP OR CONFIG_SOC_NRF54L09_ENGA_CPUAPP)
if(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP OR CONFIG_SOC_NRF54L09_ENGA_CPUAPP)
zephyr_compile_definitions(NRF_SKIP_TAMPC_SETUP)
endif()
@ -250,8 +247,6 @@ mdk_svd_ifdef(CONFIG_SOC_NRF54L10_CPUAPP nrf54l10_application.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF54L10_CPUFLPR nrf54l10_flpr.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUAPP nrf54l15_application.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR nrf54l15_flpr.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUAPP nrf54lm20a_enga_application.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUFLPR nrf54lm20a_enga_flpr.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP nrf54lm20a_enga_application.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR nrf54lm20a_enga_flpr.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF9120 nrf9120.svd)

3
snippets/nordic-flpr/snippet.yml
View File

@ -12,9 +12,6 @@ boards:
/.*/nrf54l09/cpuapp/:
append:
EXTRA_DTC_OVERLAY_FILE: soc/nrf54l09_cpuapp.overlay
/.*/nrf54l20/cpuapp/:
append:
EXTRA_DTC_OVERLAY_FILE: soc/nrf54l20_cpuapp.overlay
/.*/nrf54lm20a/cpuapp/:
append:
EXTRA_DTC_OVERLAY_FILE: soc/nrf54lm20a_cpuapp.overlay

39
snippets/nordic-flpr/soc/nrf54l20_cpuapp.overlay
View File

@ -1,39 +0,0 @@
/*
* Copyright (c) 2025 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: image@1ed000 {
/* FLPR core code partition */
reg = <0x1ed000 DT_SIZE_K(64)>;
};
};
cpuflpr_sram_code_data: memory@2006fc00 {
compatible = "mmio-sram";
reg = <0x2006fc00 DT_SIZE_K(64)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2006fc00 0x10000>;
};
};
};
&uart30 {
status = "reserved";
};
&cpuflpr_vpr {
execution-memory = <&cpuflpr_sram_code_data>;
source-memory = <&cpuflpr_code_partition>;
};
&cpuapp_vevif_tx {
status = "okay";
};

6
soc/nordic/nrf54l/Kconfig
View File

@ -37,9 +37,6 @@ config SOC_NRF54L15_CPUAPP
select SOC_COMPATIBLE_NRF54L15
select SOC_COMPATIBLE_NRF54L15_CPUAPP
config SOC_NRF54L20_ENGA_CPUAPP
select SOC_NRF54L_CPUAPP_COMMON
config SOC_NRF54LM20A_ENGA_CPUAPP
select SOC_NRF54L_CPUAPP_COMMON
select SOC_COMPATIBLE_NRF54LM20A
@ -57,9 +54,6 @@ config SOC_NRF54L10_CPUFLPR
config SOC_NRF54L15_CPUFLPR
select RISCV_CORE_NORDIC_VPR
config SOC_NRF54L20_ENGA_CPUFLPR
select RISCV_CORE_NORDIC_VPR
config SOC_NRF54LM20A_ENGA_CPUFLPR
select RISCV_CORE_NORDIC_VPR

11
soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuapp
View File

@ -1,11 +0,0 @@
# Nordic Semiconductor nRF54L20 MCU
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_NRF54L20_ENGA_CPUAPP
config NUM_IRQS
default 290
endif # SOC_NRF54L20_ENGA_CPUAPP

11
soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuflpr
View File

@ -1,11 +0,0 @@
# Nordic Semiconductor nRF54L20 MCU
# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_NRF54L20_ENGA_CPUFLPR
config NUM_IRQS
default 306
endif # SOC_NRF54L20_ENGA_CPUFLPR

25
soc/nordic/nrf54l/Kconfig.soc
View File

@ -81,30 +81,6 @@ config SOC_NRF54L15_CPUFLPR
help
NRF54L15 CPUFLPR
config SOC_NRF54L20
bool
select SOC_SERIES_NRF54LX
help
NRF54L20
config SOC_NRF54L20_ENGA
bool
select SOC_NRF54L20
help
NRF54L20 ENGA
config SOC_NRF54L20_ENGA_CPUAPP
bool
select SOC_NRF54L20_ENGA
help
NRF54L20 ENGA CPUAPP
config SOC_NRF54L20_ENGA_CPUFLPR
bool
select SOC_NRF54L20_ENGA
help
NRF54L20 ENGA CPUFLPR
config SOC_NRF54LM20A
bool
select SOC_SERIES_NRF54LX
@ -134,5 +110,4 @@ config SOC
default "nrf54l09" if SOC_NRF54L09
default "nrf54l10" if SOC_NRF54L10
default "nrf54l15" if SOC_NRF54L15
default "nrf54l20" if SOC_NRF54L20
default "nrf54lm20a" if SOC_NRF54LM20A

2
soc/nordic/nrf54l/Kconfig.sysbuild
View File

@ -1,7 +1,7 @@
# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_NRF54L09_ENGA_CPUFLPR || SOC_NRF54L15_CPUFLPR || SOC_NRF54L20_ENGA_CPUFLPR || SOC_NRF54LM20A_ENGA_CPUFLPR
if SOC_NRF54L09_ENGA_CPUFLPR || SOC_NRF54L15_CPUFLPR || SOC_NRF54LM20A_ENGA_CPUFLPR
config HAS_NORDIC_VPR_LAUNCHER_IMAGE
default y

13
soc/nordic/soc.yml
View File

@ -37,10 +37,6 @@ family:
cpuclusters:
- name: cpuapp
- name: cpuflpr
- name: nrf54l20
cpuclusters:
- name: cpuapp
- name: cpuflpr
- name: nrf54lm20a
cpuclusters:
- name: cpuapp
@ -125,9 +121,6 @@ runners:
- nrf54l15/cpuapp
- nrf54l15/cpuapp/ns
- nrf54l15/cpuflpr
- qualifiers:
- nrf54l20/cpuapp
- nrf54l20/cpuflpr
- qualifiers:
- nrf54lm20a/cpuapp
- nrf54lm20a/cpuflpr
@ -194,9 +187,6 @@ runners:
- nrf54l15/cpuapp
- nrf54l15/cpuapp/ns
- nrf54l15/cpuflpr
- qualifiers:
- nrf54l20/cpuapp
- nrf54l20/cpuflpr
- qualifiers:
- nrf54lm20a/cpuapp
- nrf54lm20a/cpuflpr
@ -263,9 +253,6 @@ runners:
- nrf54l15/cpuapp
- nrf54l15/cpuapp/ns
- nrf54l15/cpuflpr
- qualifiers:
- nrf54l20/cpuapp
- nrf54l20/cpuflpr
- qualifiers:
- nrf54lm20a/cpuapp
- nrf54lm20a/cpuflpr