diff --git a/include/zephyr/dt-bindings/clock/stm32f410_clock.h b/include/zephyr/dt-bindings/clock/stm32f410_clock.h
index e785abec0c3..951861dc32a 100644
--- a/include/zephyr/dt-bindings/clock/stm32f410_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f410_clock.h
@@ -14,16 +14,16 @@
 /** DCKCFGR devices */
 #define CKDFSDM2A_SEL(val)	STM32_CLOCK(val, 1, 14, DCKCFGR_REG)
 #define CKDFSDM1A_SEL(val)	STM32_CLOCK(val, 1, 15, DCKCFGR_REG)
-#define SAI1A_SEL(val)		STM32_CLOCK(val, 2, 20, DCKCFGR_REG)
-#define SAI1B_SEL(val)		STM32_CLOCK(val, 2, 22, DCKCFGR_REG)
-#define I2S1_SEL(val)		STM32_CLOCK(val, 2, 25, DCKCFGR_REG)
-#define I2S2_SEL(val)		STM32_CLOCK(val, 2, 27, DCKCFGR_REG)
+#define SAI1A_SEL(val)		STM32_CLOCK(val, 3, 20, DCKCFGR_REG)
+#define SAI1B_SEL(val)		STM32_CLOCK(val, 3, 22, DCKCFGR_REG)
+#define I2S1_SEL(val)		STM32_CLOCK(val, 3, 25, DCKCFGR_REG)
+#define I2S2_SEL(val)		STM32_CLOCK(val, 3, 27, DCKCFGR_REG)
 #define CKDFSDM_SEL(val)	STM32_CLOCK(val, 1, 31, DCKCFGR_REG)
 
 /** DCKCFGR2 devices */
-#define I2CFMP1_SEL(val)	STM32_CLOCK(val, 1, 22, DCKCFGR2_REG)
+#define I2CFMP1_SEL(val)	STM32_CLOCK(val, 3, 22, DCKCFGR2_REG)
 #define CK48M_SEL(val)		STM32_CLOCK(val, 1, 27, DCKCFGR2_REG)
 #define SDIO_SEL(val)		STM32_CLOCK(val, 1, 28, DCKCFGR2_REG)
-#define LPTIM1_SEL(val)		STM32_CLOCK(val, 1, 30, DCKCFGR2_REG)
+#define LPTIM1_SEL(val)		STM32_CLOCK(val, 3, 30, DCKCFGR2_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32f427_clock.h b/include/zephyr/dt-bindings/clock/stm32f427_clock.h
index e534f21c2d7..46370be53a0 100644
--- a/include/zephyr/dt-bindings/clock/stm32f427_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f427_clock.h
@@ -13,8 +13,8 @@
 /** DCKCFGR devices */
 #define CKDFSDM2A_SEL(val)	STM32_CLOCK(val, 1, 14, DCKCFGR_REG)
 #define CKDFSDM1A_SEL(val)	STM32_CLOCK(val, 1, 15, DCKCFGR_REG)
-#define SAI1A_SEL(val)		STM32_CLOCK(val, 2, 20, DCKCFGR_REG)
-#define SAI1B_SEL(val)		STM32_CLOCK(val, 2, 22, DCKCFGR_REG)
+#define SAI1A_SEL(val)		STM32_CLOCK(val, 3, 20, DCKCFGR_REG)
+#define SAI1B_SEL(val)		STM32_CLOCK(val, 3, 22, DCKCFGR_REG)
 #define CLK48M_SEL(val)		STM32_CLOCK(val, 1, 27, DCKCFGR_REG)
 #define SDMMC_SEL(val)		STM32_CLOCK(val, 1, 28, DCKCFGR_REG)
 #define DSI_SEL(val)		STM32_CLOCK(val, 1, 29, DCKCFGR_REG)