drivers: pwm: add a SAM0 TC based PWM driver
This runs the Timer/counter in 'normal' PWM mode (for 8-bits) and in 'match' PWM mode (for 16-bits). Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
This commit is contained in:
Teresa Zepeda Ventura
Benjamin Cabé
parent
b98bedeeb9
commit
830fe6ec19
@ -26,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_RV32M1_TPM pwm_rv32m1_tpm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MAX32 pwm_max32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MAX32 pwm_max32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_TPM pwm_mcux_tpm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_TPM pwm_mcux_tpm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM0_TCC pwm_sam0_tcc.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM0_TCC pwm_sam0_tcc.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM0_TC pwm_sam0_tc.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NPCX pwm_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NPCX pwm_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_XLNX_AXI_TIMER pwm_xlnx_axi_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_XLNX_AXI_TIMER pwm_xlnx_axi_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_PWT pwm_mcux_pwt.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_PWT pwm_mcux_pwt.c)
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@ -74,6 +74,8 @@ source "drivers/pwm/Kconfig.mcux_tpm"
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source "drivers/pwm/Kconfig.sam0"
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source "drivers/pwm/Kconfig.sam0"
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source "drivers/pwm/Kconfig.sam0_tc"
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source "drivers/pwm/Kconfig.npcx"
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source "drivers/pwm/Kconfig.npcx"
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source "drivers/pwm/Kconfig.xlnx"
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source "drivers/pwm/Kconfig.xlnx"
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17
drivers/pwm/Kconfig.sam0_tc
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17
drivers/pwm/Kconfig.sam0_tc
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@ -0,0 +1,17 @@
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# Atmel SAM0 TCC as PWM configuration
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# Copyright (c) 2020 Google LLC
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# SPDX-License-Identifier: Apache-2.0
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config PWM_SAM0_TC
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bool "Atmel SAM0 MCU Family TC PWM Driver"
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default y
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depends on DT_HAS_ATMEL_SAM0_TC_PWM_ENABLED
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help
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Enable PWM driver for Atmel SAM0 MCUs using the TC timer/counter.
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config PWM_TC_INIT_PRIORITY
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int "Init Priority"
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default 50
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help
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Device driver initialization priority
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214
drivers/pwm/pwm_sam0_tc.c
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214
drivers/pwm/pwm_sam0_tc.c
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@ -0,0 +1,214 @@
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/*
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* Copyright (c) 2024 Daikin Comfort Technologies North America, Inc.
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*
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* Heavily based on pwm_sam0_tcc.c, which is:
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* Copyright (c) 2020 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* PWM driver using the SAM0 Timer/Counter (TC) Supports the SAMD21 and SAMD5x series,
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* 8 and 16 bit counter size is supported.
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*
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* The 8-bit counter operates in Normal PWM (NPWM) mode, it supports pulse width and period
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* values between 0 and 255. It is ideal for applications requiring moderate frequency PWM,
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* however, it is not suitable for high-precision or low-frequency applications.
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*
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* The 16-bit counter operates in Match PWM (MPWM) mode to generate the PWM signal.
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* this mode sacrifices the timer's CC0 channel in order to achieve pulse width modulation.
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*/
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#define DT_DRV_COMPAT atmel_sam0_tc_pwm
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <errno.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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/* Static configuration */
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struct pwm_sam0_config {
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Tc *regs;
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const struct pinctrl_dev_config *pcfg;
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uint8_t channels;
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uint8_t counter_size;
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uint16_t prescaler;
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uint32_t freq;
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#ifdef MCLK
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volatile uint32_t *mclk;
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uint32_t mclk_mask;
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uint16_t gclk_id;
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#else
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uint32_t pm_apbcmask;
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uint16_t gclk_clkctrl_id;
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#endif
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};
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#define COUNTER_8BITS 8U
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/* Wait for the peripheral to finish all commands */
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static void wait_synchronization(Tc *regs, uint8_t counter_size)
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{
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if (COUNTER_8BITS == counter_size) {
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while (regs->COUNT8.SYNCBUSY.reg != 0) {
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}
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} else {
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while (regs->COUNT16.SYNCBUSY.reg != 0) {
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}
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}
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}
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static int pwm_sam0_get_cycles_per_sec(const struct device *dev,
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uint32_t channel, uint64_t *cycles)
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{
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const struct pwm_sam0_config *const cfg = dev->config;
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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*cycles = cfg->freq;
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return 0;
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}
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static int pwm_sam0_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles,
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uint32_t pulse_cycles, pwm_flags_t flags)
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{
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const struct pwm_sam0_config *const cfg = dev->config;
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Tc *regs = cfg->regs;
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uint8_t counter_size = cfg->counter_size;
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uint32_t top = 1 << counter_size;
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uint32_t invert_mask = 1 << channel;
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bool invert = ((flags & PWM_POLARITY_INVERTED) != 0);
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bool inverted;
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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if (period_cycles >= top || pulse_cycles >= top) {
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return -EINVAL;
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}
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/*
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* Update the buffered width and period. These will be automatically
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* loaded on the next cycle.
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*/
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if (COUNTER_8BITS == counter_size) {
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inverted = ((regs->COUNT8.DRVCTRL.vec.INVEN & invert_mask) != 0);
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regs->COUNT8.CCBUF[channel].reg = TC_COUNT8_CCBUF_CCBUF(pulse_cycles);
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regs->COUNT8.PERBUF.reg = TC_COUNT8_PERBUF_PERBUF(period_cycles);
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wait_synchronization(regs, counter_size);
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if (invert != inverted) {
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regs->COUNT8.CTRLA.bit.ENABLE = 0;
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wait_synchronization(regs, counter_size);
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regs->COUNT8.DRVCTRL.vec.INVEN ^= invert_mask;
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regs->COUNT8.CTRLA.bit.ENABLE = 1;
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wait_synchronization(regs, counter_size);
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}
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} else {
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inverted = ((regs->COUNT16.DRVCTRL.vec.INVEN & invert_mask) != 0);
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regs->COUNT16.CCBUF[0].reg = TC_COUNT16_CCBUF_CCBUF(period_cycles);
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regs->COUNT16.CCBUF[1].reg = TC_COUNT16_CCBUF_CCBUF(pulse_cycles);
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wait_synchronization(regs, counter_size);
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if (invert != inverted) {
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regs->COUNT16.CTRLA.bit.ENABLE = 0;
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wait_synchronization(regs, counter_size);
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regs->COUNT16.DRVCTRL.vec.INVEN ^= invert_mask;
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regs->COUNT16.CTRLA.bit.ENABLE = 1;
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wait_synchronization(regs, counter_size);
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}
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}
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return 0;
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}
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static int pwm_sam0_init(const struct device *dev)
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{
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const struct pwm_sam0_config *const cfg = dev->config;
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int retval;
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Tc *regs = cfg->regs;
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uint8_t counter_size = cfg->counter_size;
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/* Enable the clocks */
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#ifdef MCLK
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GCLK->PCHCTRL[cfg->gclk_id].reg =
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GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
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*cfg->mclk |= cfg->mclk_mask;
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#else
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GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
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GCLK_CLKCTRL_CLKEN;
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PM->APBCMASK.reg |= cfg->pm_apbcmask;
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#endif
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retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (retval < 0) {
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return retval;
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}
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if (COUNTER_8BITS == counter_size) {
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regs->COUNT8.CTRLA.bit.SWRST = 1;
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wait_synchronization(regs, counter_size);
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regs->COUNT8.CTRLA.reg = cfg->prescaler | TC_CTRLA_MODE_COUNT8 |
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TC_CTRLA_PRESCSYNC_PRESC;
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regs->COUNT8.WAVE.reg = TC_WAVE_WAVEGEN_NPWM;
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regs->COUNT8.PER.reg = TC_COUNT8_PER_PER(1);
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regs->COUNT8.CTRLA.bit.ENABLE = 1;
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wait_synchronization(regs, counter_size);
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} else {
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regs->COUNT16.CTRLA.bit.SWRST = 1;
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wait_synchronization(regs, counter_size);
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regs->COUNT16.CTRLA.reg = cfg->prescaler | TC_CTRLA_MODE_COUNT16 |
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TC_CTRLA_PRESCSYNC_PRESC;
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regs->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MPWM;
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regs->COUNT16.CC[0].reg = TC_COUNT16_CC_CC(1);
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regs->COUNT16.CTRLA.bit.ENABLE = 1;
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wait_synchronization(regs, cfg->counter_size);
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}
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return 0;
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}
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static DEVICE_API(pwm, pwm_sam0_driver_api) = {
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.set_cycles = pwm_sam0_set_cycles,
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.get_cycles_per_sec = pwm_sam0_get_cycles_per_sec,
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};
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#ifdef MCLK
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#define PWM_SAM0_INIT_CLOCKS(inst) \
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.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst), \
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.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)), \
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.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch)
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#else
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#define PWM_SAM0_INIT_CLOCKS(inst) \
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.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, pm, bit)), \
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.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, clkctrl_id)
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#endif
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#define PWM_SAM0_INIT(inst) \
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PINCTRL_DT_INST_DEFINE(inst); \
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static const struct pwm_sam0_config pwm_sam0_config_##inst = { \
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.regs = (Tc *)DT_INST_REG_ADDR(inst), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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.channels = DT_INST_PROP(inst, channels), \
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.counter_size = DT_INST_PROP(inst, counter_size), \
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.prescaler = UTIL_CAT(TC_CTRLA_PRESCALER_DIV, DT_INST_PROP(inst, prescaler)), \
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.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / DT_INST_PROP(inst, prescaler), \
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PWM_SAM0_INIT_CLOCKS(inst), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &pwm_sam0_init, NULL, NULL, &pwm_sam0_config_##inst, \
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POST_KERNEL, CONFIG_PWM_TC_INIT_PRIORITY, &pwm_sam0_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_SAM0_INIT)
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