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drivers: gpio: add support for mspm0L series banks

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All the HAL API/wrapper depends on PINCM indexing, which cannot
be derived from neither pin number nor the address offset.

With current approach, update the LUT table of possible PINCM's
for L series with GPIO A, B and C banks.

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
This commit is contained in:
Parthiban Nallathambi 2025-05-29 20:21:20 +05:30 committed by Anas Nashif
parent 4e78996e16
commit 7a70fab29b
1 changed files with 41 additions and 0 deletions
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41
drivers/gpio/gpio_mspm0.c
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@ -47,6 +47,18 @@ static uint32_t gpioa_pincm_lut[NUM_GPIOA_PIN] = {
IOMUX_PINCM54, IOMUX_PINCM55, IOMUX_PINCM59, IOMUX_PINCM60, IOMUX_PINCM3, IOMUX_PINCM4,
IOMUX_PINCM5, IOMUX_PINCM6,
};
#elif CONFIG_SOC_SERIES_MSPM0L /* if CONFIG_SOC_SERIES_MSPM0L */
#define GPIOA_NODE DT_NODELABEL(gpioa)
#define NUM_GPIOA_PIN 31
#define gpioa_pins NUM_GPIOA_PIN
static uint32_t gpioa_pincm_lut[NUM_GPIOA_PIN] = {
IOMUX_PINCM1, IOMUX_PINCM2, IOMUX_PINCM7, IOMUX_PINCM8, IOMUX_PINCM9, IOMUX_PINCM10,
IOMUX_PINCM11, IOMUX_PINCM14, IOMUX_PINCM19, IOMUX_PINCM20, IOMUX_PINCM25, IOMUX_PINCM26,
IOMUX_PINCM38, IOMUX_PINCM39, IOMUX_PINCM40, IOMUX_PINCM41, IOMUX_PINCM42, IOMUX_PINCM49,
IOMUX_PINCM50, IOMUX_PINCM51, IOMUX_PINCM52, IOMUX_PINCM56, IOMUX_PINCM57, IOMUX_PINCM67,
IOMUX_PINCM68, IOMUX_PINCM69, IOMUX_PINCM73, IOMUX_PINCM74, IOMUX_PINCM3, IOMUX_PINCM4,
IOMUX_PINCM5
};
#else
#error "Series lookup table not supported"
#endif /* if CONFIG_SOC_SERIES_MSPM0G */
@ -64,9 +76,33 @@ static uint32_t gpiob_pincm_lut[NUM_GPIOB_PIN] = {
IOMUX_PINCM44, IOMUX_PINCM45, IOMUX_PINCM48, IOMUX_PINCM49, IOMUX_PINCM50, IOMUX_PINCM51,
IOMUX_PINCM52, IOMUX_PINCM56, IOMUX_PINCM57, IOMUX_PINCM58,
};
#elif CONFIG_SOC_SERIES_MSPM0L /* if CONFIG_SOC_SERIES_MSPM0L */
#define GPIOB_NODE DT_NODELABEL(gpiob)
#define NUM_GPIOB_PIN 32
#define gpiob_pins NUM_GPIOB_PIN
static uint32_t gpiob_pincm_lut[NUM_GPIOB_PIN] = {
IOMUX_PINCM12, IOMUX_PINCM13, IOMUX_PINCM15, IOMUX_PINCM16, IOMUX_PINCM17, IOMUX_PINCM18,
IOMUX_PINCM27, IOMUX_PINCM28, IOMUX_PINCM29, IOMUX_PINCM30, IOMUX_PINCM31, IOMUX_PINCM32,
IOMUX_PINCM33, IOMUX_PINCM34, IOMUX_PINCM35, IOMUX_PINCM36, IOMUX_PINCM37, IOMUX_PINCM53,
IOMUX_PINCM54, IOMUX_PINCM55, IOMUX_PINCM62, IOMUX_PINCM63, IOMUX_PINCM64, IOMUX_PINCM65,
IOMUX_PINCM66, IOMUX_PINCM70, IOMUX_PINCM71, IOMUX_PINCM72, IOMUX_PINCM21, IOMUX_PINCM22,
IOMUX_PINCM23, IOMUX_PINCM24
};
#endif /* CONFIG_SOC_SERIES_MSPM0G */
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioc), okay)
#define GPIOC_NODE DT_NODELABEL(gpioc)
#ifdef CONFIG_SOC_SERIES_MSPM0L
#define NUM_GPIOC_PIN 10
#define gpioc_pins NUM_GPIOC_PIN
static uint32_t gpioc_pincm_lut[NUM_GPIOC_PIN] = {
IOMUX_PINCM43, IOMUX_PINCM44, IOMUX_PINCM45, IOMUX_PINCM46, IOMUX_PINCM47,
IOMUX_PINCM48, IOMUX_PINCM58, IOMUX_PINCM59, IOMUX_PINCM60, IOMUX_PINCM61,
};
#endif /* CONFIG_SOC_SERIES */
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioc), okay) */
static int gpio_mspm0_port_get_raw(const struct device *port, uint32_t *value)
{
const struct gpio_mspm0_config *config = port->config;
@ -236,6 +272,7 @@ static void gpio_mspm0_isr(const struct device *port)
const struct device *dev_list[] = {
DEVICE_DT_GET_OR_NULL(GPIOA_NODE),
DEVICE_DT_GET_OR_NULL(GPIOB_NODE),
DEVICE_DT_GET_OR_NULL(GPIOC_NODE),
};
for (uint8_t i = 0; i < ARRAY_SIZE(dev_list); i++) {
@ -356,3 +393,7 @@ GPIO_DEVICE_INIT_MSPM0(a);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay)
GPIO_DEVICE_INIT_MSPM0(b);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioc), okay)
GPIO_DEVICE_INIT_MSPM0(c);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioc), okay) */