From 75a2f3e484bc3d626bfbdd169c4247fe924ef8a0 Mon Sep 17 00:00:00 2001
From: Simon Guinot <simon.guinot@seagate.com>
Date: Mon, 11 May 2020 19:01:47 +0200
Subject: [PATCH] dts: lpc11u6x: add node and binding for on-chip EEPROM

This patch adds the DT nodes and binding for the on-chip EEPROM found
on the LPC11U6x MCUs.

Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
---
 dts/arm/nxp/nxp_lpc11u6x.dtsi             | 15 ++++++++++++++-
 dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml |  8 ++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)
 create mode 100644 dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml

diff --git a/dts/arm/nxp/nxp_lpc11u6x.dtsi b/dts/arm/nxp/nxp_lpc11u6x.dtsi
index 5e026714d5e..882a03d7895 100644
--- a/dts/arm/nxp/nxp_lpc11u6x.dtsi
+++ b/dts/arm/nxp/nxp_lpc11u6x.dtsi
@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2020, Seagate
+ * Copyright (c) 2020, Seagate Technology LLC
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <arm/armv6-m.dtsi>
 #include <dt-bindings/clock/lpc11u6x_clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <mem.h>
 
 / {
 	cpus {
@@ -37,6 +38,18 @@
 			compatible = "soc-nv-flash";
 		};
 
+		/* On-chip EEPROM. */
+		eeprom0: eeprom_0 {
+			compatible = "nxp,lpc11u6x-eeprom";
+			label = "EEPROM_0";
+			/*
+			 * For some reasons, the IAP commands don't allow to
+			 * reach the last 64 bytes of the EEPROM.
+			 */
+			size = <(DT_SIZE_K(4) - 64)>;
+			status = "okay";
+		};
+
 		/* PIO0_0 to PIO0_23. */
 		pinmux0: pinmux@40044000 {
 			compatible = "nxp,lpc11u6x-pinmux";
diff --git a/dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml b/dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml
new file mode 100644
index 00000000000..ddca97882a7
--- /dev/null
+++ b/dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC11U6X on-chip EEPROM node
+
+compatible: "nxp,lpc11u6x-eeprom"
+
+include: eeprom-base.yaml