diff --git a/drivers/clock_control/clock_stm32f1.c b/drivers/clock_control/clock_stm32f1.c
index 762aab38ce2..8beb8812893 100644
--- a/drivers/clock_control/clock_stm32f1.c
+++ b/drivers/clock_control/clock_stm32f1.c
@@ -49,12 +49,12 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
 	 * 9  -> LL_RCC_PLL_MUL_9   -> 0x001C0000
 	 * 13 -> LL_RCC_PLL_MUL_6_5 -> 0x00340000
 	 */
-	pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
+	pllinit->PLLMul = ((STM32_PLL_MULTIPLIER - 2)
 					<< RCC_CFGR_PLLMULL_Pos);
 
 #ifdef CONFIG_SOC_STM32F10X_DENSITY_DEVICE
 	/* PLL prediv */
-#ifdef CONFIG_CLOCK_STM32_PLL_XTPRE
+#ifdef STM32_PLL_XTPRE
 	/*
 	 * SOC_STM32F10X_DENSITY_DEVICE:
 	 * PLLXPTRE (depends on PLL source HSE)
@@ -68,7 +68,7 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
 	 * HSE used as direct PLL source
 	 */
 	pllinit->Prediv = LL_RCC_PREDIV_DIV_1;
-#endif /* CONFIG_CLOCK_STM32_PLL_XTPRE */
+#endif /* STM32_PLL_XTPRE */
 #else
 	/*
 	 * SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
@@ -78,7 +78,7 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
 	 * ...
 	 * 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
 	 */
-	pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1;
+	pllinit->Prediv = STM32_PLL_PREDIV1 - 1;
 #endif /* CONFIG_SOC_STM32F10X_DENSITY_DEVICE */
 }
 
diff --git a/include/drivers/clock_control/stm32_clock_control.h b/include/drivers/clock_control/stm32_clock_control.h
index c0a18d6e9f2..9d467f714cc 100644
--- a/include/drivers/clock_control/stm32_clock_control.h
+++ b/include/drivers/clock_control/stm32_clock_control.h
@@ -82,6 +82,18 @@
 #define STM32_PLL_R_DIVISOR	CONFIG_CLOCK_STM32_PLL_R_DIVISOR
 #endif
 
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
+#define STM32_PLL_XTPRE		DT_PROP(DT_NODELABEL(pll), xtre)
+#define STM32_PLL_MULTIPLIER	DT_PROP(DT_NODELABEL(pll), mul)
+#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
+#define STM32_PLL_MULTIPLIER	DT_PROP(DT_NODELABEL(pll), mul)
+#define STM32_PLL_PREDIV1	DT_PROP(DT_NODELABEL(pll), prediv)
+#else
+#define STM32_PLL_XTPRE		CONFIG_CLOCK_STM32_PLL_XTPRE
+#define STM32_PLL_MULTIPLIER	CONFIG_CLOCK_STM32_PLL_MULTIPLIER
+#define STM32_PLL_PREDIV1	CONFIG_CLOCK_STM32_PLL_PREDIV1
+#endif
+
 #define DT_RCC_CLOCKS_CTRL	DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
 
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay) && \
@@ -105,20 +117,18 @@
 
 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
 	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
-	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay)) && \
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay) || \
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)) && \
 	DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
 #define STM32_PLL_SRC_MSI	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
 #define STM32_PLL_SRC_HSI	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
 #define STM32_PLL_SRC_HSE	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
+#define STM32_PLL_SRC_PLL2	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
 #else
 #define STM32_PLL_SRC_MSI	CONFIG_CLOCK_STM32_PLL_SRC_MSI
 #define STM32_PLL_SRC_HSI	CONFIG_CLOCK_STM32_PLL_SRC_HSI
 #define STM32_PLL_SRC_HSE	CONFIG_CLOCK_STM32_PLL_SRC_HSE
-#endif
-
-#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay)
-#define STM32_PLL_SRC_PLL2	DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(pll)), DT_NODELABEL(pll2))
-#else
 #define STM32_PLL_SRC_PLL2	CONFIG_CLOCK_STM32_PLL_SRC_PLL2
 #endif