From 67edf2292a94eaf3f155ecb05f59f038e3c35a92 Mon Sep 17 00:00:00 2001 From: Marcin Wierzbicki Date: Wed, 26 Mar 2025 12:06:42 +0100 Subject: [PATCH] boards: nxp: add support for S32K148 evaluation board Support for NXP S32K148 evaluation board (s32k148_evb). Adapt samples: adc_dt, adc_sequence. Adapt tests: adc_api, gpio_basic_api, gpio_hogs. Signed-off-by: Marcin Wierzbicki --- boards/nxp/s32k148_evb/Kconfig.defconfig | 20 ++ boards/nxp/s32k148_evb/Kconfig.s32k148_evb | 6 + boards/nxp/s32k148_evb/board.cmake | 12 ++ boards/nxp/s32k148_evb/board.yml | 6 + .../nxp/s32k148_evb/doc/img/s32k148_evb.webp | Bin 0 -> 26716 bytes boards/nxp/s32k148_evb/doc/index.rst | 162 ++++++++++++++++ .../nxp/s32k148_evb/s32k148_evb-pinctrl.dtsi | 87 +++++++++ boards/nxp/s32k148_evb/s32k148_evb.dts | 181 ++++++++++++++++++ boards/nxp/s32k148_evb/s32k148_evb.yaml | 22 +++ boards/nxp/s32k148_evb/s32k148_evb_defconfig | 13 ++ dts/arm/nxp/nxp_s32k148.dtsi | 76 ++++++++ .../dt-bindings/clock/nxp_s32k148_clock.h | 100 ++++++++++ .../adc/adc_dt/boards/s32k148_evb.overlay | 38 ++++ samples/drivers/adc/adc_dt/sample.yaml | 1 + .../adc_sequence/boards/s32k148_evb.overlay | 38 ++++ samples/drivers/adc/adc_sequence/sample.yaml | 1 + .../adc/adc_api/boards/s32k148_evb.overlay | 42 ++++ .../gpio_basic_api/boards/s32k148_evb.overlay | 13 ++ .../gpio/gpio_hogs/boards/s32k148_evb.overlay | 35 ++++ west.yml | 2 +- 20 files changed, 854 insertions(+), 1 deletion(-) create mode 100644 boards/nxp/s32k148_evb/Kconfig.defconfig create mode 100644 boards/nxp/s32k148_evb/Kconfig.s32k148_evb create mode 100644 boards/nxp/s32k148_evb/board.cmake create mode 100644 boards/nxp/s32k148_evb/board.yml create mode 100644 boards/nxp/s32k148_evb/doc/img/s32k148_evb.webp create mode 100644 boards/nxp/s32k148_evb/doc/index.rst create mode 100644 boards/nxp/s32k148_evb/s32k148_evb-pinctrl.dtsi create mode 100644 boards/nxp/s32k148_evb/s32k148_evb.dts create mode 100644 boards/nxp/s32k148_evb/s32k148_evb.yaml create mode 100644 boards/nxp/s32k148_evb/s32k148_evb_defconfig create mode 100644 dts/arm/nxp/nxp_s32k148.dtsi create mode 100644 include/zephyr/dt-bindings/clock/nxp_s32k148_clock.h create mode 100644 samples/drivers/adc/adc_dt/boards/s32k148_evb.overlay create mode 100644 samples/drivers/adc/adc_sequence/boards/s32k148_evb.overlay create mode 100644 tests/drivers/adc/adc_api/boards/s32k148_evb.overlay create mode 100644 tests/drivers/gpio/gpio_basic_api/boards/s32k148_evb.overlay create mode 100644 tests/drivers/gpio/gpio_hogs/boards/s32k148_evb.overlay diff --git a/boards/nxp/s32k148_evb/Kconfig.defconfig b/boards/nxp/s32k148_evb/Kconfig.defconfig new file mode 100644 index 00000000000..7a162d20ce4 --- /dev/null +++ b/boards/nxp/s32k148_evb/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_S32K148_EVB + +if SERIAL + +config UART_CONSOLE + default y + +endif # SERIAL + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_S32K148_EVB diff --git a/boards/nxp/s32k148_evb/Kconfig.s32k148_evb b/boards/nxp/s32k148_evb/Kconfig.s32k148_evb new file mode 100644 index 00000000000..50f931e7b76 --- /dev/null +++ b/boards/nxp/s32k148_evb/Kconfig.s32k148_evb @@ -0,0 +1,6 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_S32K148_EVB + select SOC_S32K148 + select SOC_PART_NUMBER_FS32K148HAT0MLUT diff --git a/boards/nxp/s32k148_evb/board.cmake b/boards/nxp/s32k148_evb/board.cmake new file mode 100644 index 00000000000..c26e0862b29 --- /dev/null +++ b/boards/nxp/s32k148_evb/board.cmake @@ -0,0 +1,12 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink + "--device=S32K148" + "--speed=4000" + "--iface=jtag" + "--reset" + "--tool-opt=-jtagconf -1,-1" +) + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/s32k148_evb/board.yml b/boards/nxp/s32k148_evb/board.yml new file mode 100644 index 00000000000..90d9decc827 --- /dev/null +++ b/boards/nxp/s32k148_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: s32k148_evb + full_name: S32K148EVB-Q176 + vendor: nxp + socs: + - name: s32k148 diff --git a/boards/nxp/s32k148_evb/doc/img/s32k148_evb.webp b/boards/nxp/s32k148_evb/doc/img/s32k148_evb.webp new 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z_5q4Zfgsmmmp?;Oz=FSzk4s#8CGU7cc?;)TJ(Gz}jvt+Pp#TNp)j4dq&rrr8?A-FB z9O}Wa05A5zIpkLXbb)!kG*+dOUPprYq5yUe9Mfv+YVrGIf7bTW-kR2@U&fi@)u64@o~B&vEQ7UsJ^Sa69@M&5Pl9$lB&JM+Amtt891x0D5O|OZ@dT@QcT_W2)H>kN^Mx D1;uGl literal 0 HcmV?d00001 diff --git a/boards/nxp/s32k148_evb/doc/index.rst b/boards/nxp/s32k148_evb/doc/index.rst new file mode 100644 index 00000000000..8c7aac34f15 --- /dev/null +++ b/boards/nxp/s32k148_evb/doc/index.rst @@ -0,0 +1,162 @@ +.. zephyr:board:: s32k148_evb + +Overview +******** + +`NXP S32K148-Q176`_ is a low-cost evaluation and development board for general-purpose industrial +and automotive applications. +The S32K148-Q176 is based on the 32-bit Arm Cortex-M4F `NXP S32K148`_ microcontroller. +The onboard OpenSDA serial and debug adapter, running a mass storage device (MSD) bootloader +and a collection of OpenSDA Applications, offers options for serial communication, +flash programming, and run-control debugging. +It is a bridge between a USB host and the embedded target processor. + +Hardware +******** + +- NXP S32K148 + + - Arm Cortex-M4F @ up to 112 Mhz + - 1.5 MB Flash + - 256 KB SRAM + - up to 127 I/Os + - 3x FlexCAN with FD + - eDMA, 12-bit ADC, MPU, ECC and more. + +- Interfaces + + - CAN, LIN, UART/SCI + - Ethernet connector compatible with different ethernet daughter cards + - 2 touchpads, potentiometer, user RGB LED and 2 buttons. + +More information about the hardware and design resources can be found at +`NXP S32K148-Q176`_ website. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +This board has 5 GPIO ports named from ``gpioa`` to ``gpioe``. + +Pin control can be further configured from your application overlay by adding +children nodes with the desired pinmux configuration to the singleton node +``pinctrl``. Supported properties are described in +:zephyr_file:`dts/bindings/pinctrl/nxp,port-pinctrl.yaml`. + +LEDs +---- + +The NXP S32K148-Q176 board has one user RGB LED that can be used either as a GPIO +LED or as a PWM LED. + +.. table:: RGB LED as GPIO LED + + +-----------------+------------------+----------------+-------+ + | Devicetree node | Devicetree alias | Label | Pin | + +=================+==================+================+=======+ + | led1_red | led0 | LED1_RGB_RED | PTE21 | + +-----------------+------------------+----------------+-------+ + | led1_green | led1 | LED1_RGB_GREEN | PTE22 | + +-----------------+------------------+----------------+-------+ + | led1_blue | led2 | LED1_RGB_BLUE | PTE23 | + +-----------------+------------------+----------------+-------+ + +.. table:: RGB LED as PWM LED + + +-----------------+--------------------------+--------------------+------------------+ + | Devicetree node | Devicetree alias | Label | Pin | + +=================+==========================+====================+==================+ + | led1_red_pwm | pwm-led0 / red-pwm-led | LED1_RGB_RED_PWM | PTE21 / FTM4_CH1 | + +-----------------+--------------------------+--------------------+------------------+ + | led1_green_pwm | pwm-led1 / green-pwm-led | LED1_RGB_GREEN_PWM | PTE22 / FTM4_CH2 | + +-----------------+--------------------------+--------------------+------------------+ + | led1_blue_pwm | pwm-led2 / blue-pwm-led | LED1_RGB_BLUE_PWM | PTE23 / FTM4_CH3 | + +-----------------+--------------------------+--------------------+------------------+ + +The user can control the LEDs in any way. An output of ``0`` illuminates the LED. + +Buttons +------- + +The NXP S32K148-Q176 board has two user buttons: + ++-----------------+-------+-------+ +| Devicetree node | Label | Pin | ++=================+=======+=======+ +| sw0 / button_3 | SW3 | PTC12 | ++-----------------+-------+-------+ +| sw1 / button_4 | SW4 | PTC13 | ++-----------------+-------+-------+ + +Serial Console +============== + +The serial console is provided via ``lpuart1`` on the OpenSDA adapter. + ++------+--------------+ +| Pin | Pin Function | ++======+==============+ +| PTC7 | LPUART1_TX | ++------+--------------+ +| PTC6 | LPUART1_RX | ++------+--------------+ + +System Clock +============ + +The Arm Cortex-M4F core is configured to run at 80 MHz (RUN mode). + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``s32k148_evb`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +This board configuration supports `SEGGER J-Link`_ West runner for flashing and +debugging applications. Follow the steps described in :ref:`jlink-debug-host-tools`, +to setup the flash and debug host tools for this runner. + +Flashing +======== + +Run the ``west flash`` command to flash the application using SEGGER J-Link. + +Debugging +========= + +Run the ``west debug`` command to start a GDB session using SEGGER J-Link. + +Configuring a Console +===================== + +We will use OpenSDA as a USB-to-serial adapter for the serial console. + +Use the following settings with your serial terminal of choice (minicom, putty, etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +.. include:: ../../common/board-footer.rst + :start-after: nxp-board-footer + +References +********** + +.. target-notes:: + +.. _NXP S32K148-Q176: + https://www.nxp.com/design/design-center/development-boards-and-designs/automotive-development-platforms/s32k-mcu-platforms/s32k148-q176-evaluation-board-for-automotive-general-purpose:S32K148EVB + +.. _NXP S32K148: + https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k1-microcontrollers-for-automotive-general-purpose:S32K1 + +.. _SEGGER J-Link: + https://wiki.segger.com/S32Kxxx diff --git a/boards/nxp/s32k148_evb/s32k148_evb-pinctrl.dtsi b/boards/nxp/s32k148_evb/s32k148_evb-pinctrl.dtsi new file mode 100644 index 00000000000..181018407d8 --- /dev/null +++ b/boards/nxp/s32k148_evb/s32k148_evb-pinctrl.dtsi @@ -0,0 +1,87 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + lpuart0_default: lpuart0_default { + group0 { + pinmux = , ; + drive-strength = "low"; + }; + }; + + lpuart1_default: lpuart1_default { + group0 { + pinmux = , ; + drive-strength = "low"; + }; + }; + + lpi2c0_default: lpi2c0_default { + group1 { + pinmux = , ; + drive-strength = "low"; + }; + }; + + lpspi0_default: lpspi0_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + }; + }; + + ftm4_default: ftm4_default { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + }; + }; + + flexcan0_default: flexcan0_default { + group0 { + pinmux = , ; + drive-strength = "low"; + }; + }; + + pinmux_enet: pinmux_enet { + group1 { + pinmux = , + , + , + , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + pinmux_enet_mdio: pinmux_enet_mdio { + group0 { + pinmux = ; + drive-strength = "low"; + drive-open-drain; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; +}; diff --git a/boards/nxp/s32k148_evb/s32k148_evb.dts b/boards/nxp/s32k148_evb/s32k148_evb.dts new file mode 100644 index 00000000000..3c4f994cf4c --- /dev/null +++ b/boards/nxp/s32k148_evb/s32k148_evb.dts @@ -0,0 +1,181 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "s32k148_evb-pinctrl.dtsi" + +/ { + model = "NXP S32K148EVB"; + compatible = "nxp,s32k148_evb"; + + chosen { + zephyr,sram = &sram_l; + zephyr,flash = &flash0; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,uart-pipe = &lpuart1; + zephyr,canbus = &flexcan0; + }; + + aliases { + led0 = &led1_red; + led1 = &led1_green; + led2 = &led1_blue; + pwm-led0 = &led1_red_pwm; + pwm-led1 = &led1_green_pwm; + pwm-led2 = &led1_blue_pwm; + red-pwm-led = &led1_red_pwm; + green-pwm-led = &led1_green_pwm; + blue-pwm-led = &led1_blue_pwm; + sw0 = &button_3; + sw1 = &button_4; + i2c-0 = &lpi2c0; + }; + + leds { + compatible = "gpio-leds"; + + led1_red: led_0 { + gpios = <&gpioe 21 GPIO_ACTIVE_LOW>; + label = "LED1_RGB_RED"; + }; + + led1_green: led_1 { + gpios = <&gpioe 22 GPIO_ACTIVE_LOW>; + label = "LED1_RGB_GREEN"; + }; + + led1_blue: led_2 { + gpios = <&gpioe 23 GPIO_ACTIVE_LOW>; + label = "LED1_RGB_BLUE"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + led1_red_pwm: led_pwm_0 { + pwms = <&ftm4 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "LED1_RGB_RED_PWM"; + }; + + led1_green_pwm: led_pwm_1 { + pwms = <&ftm4 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "LED1_RGB_GREEN_PWM"; + }; + + led1_blue_pwm: led_pwm_2 { + pwms = <&ftm4 3 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "LED1_RGB_BLUE_PWM"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button_3: button_0 { + label = "SW3"; + gpios = <&gpioc 12 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + button_4: button_1 { + label = "SW4"; + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <80000000>; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&lpuart0 { + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; + current-speed = <115200>; +}; + +&lpuart1 { + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&lpi2c0 { + pinctrl-0 = <&lpi2c0_default>; + pinctrl-names = "default"; + scl-gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&lpspi0 { + pinctrl-0 = <&lpspi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ftm4 { + compatible = "nxp,ftm-pwm"; + pinctrl-0 = <&ftm4_default>; + pinctrl-names = "default"; + clock-source = "system"; + prescaler = <4>; + #pwm-cells = <3>; + status = "okay"; +}; + +/* + * The S32K148EVB board contains a UJA1132 SBC which needs to be configured via SPI. + * The factory preset forces it to normal mode though, so the CAN phy is enabled + * even without configuration. + * Therefore, we don't reference a can phy driver node here for now. + */ +&flexcan0 { + pinctrl-0 = <&flexcan0_default>; + pinctrl-names = "default"; + bitrate = <125000>; + status = "okay"; +}; + +&adc0 { + sample-time = <65>; + vref-mv = <5000>; + status = "okay"; +}; + +&adc1 { + sample-time = <65>; + vref-mv = <5000>; + status = "okay"; +}; diff --git a/boards/nxp/s32k148_evb/s32k148_evb.yaml b/boards/nxp/s32k148_evb/s32k148_evb.yaml new file mode 100644 index 00000000000..caa76f3afef --- /dev/null +++ b/boards/nxp/s32k148_evb/s32k148_evb.yaml @@ -0,0 +1,22 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32k148_evb +name: NXP S32K148EVB-Q176 +vendor: nxp +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr +supported: + - mpu + - gpio + - uart + - pinctrl + - pwm + - can + - watchdog + - counter + - adc diff --git a/boards/nxp/s32k148_evb/s32k148_evb_defconfig b/boards/nxp/s32k148_evb/s32k148_evb_defconfig new file mode 100644 index 00000000000..08e047dd7bb --- /dev/null +++ b/boards/nxp/s32k148_evb/s32k148_evb_defconfig @@ -0,0 +1,13 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +# Run from internal program flash +CONFIG_XIP=y + +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y diff --git a/dts/arm/nxp/nxp_s32k148.dtsi b/dts/arm/nxp/nxp_s32k148.dtsi new file mode 100644 index 00000000000..7f09ed1ce06 --- /dev/null +++ b/dts/arm/nxp/nxp_s32k148.dtsi @@ -0,0 +1,76 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-m4f"; + }; + }; + + soc { + /* + * SRAM_L and SRAM_U ranges form a contiguous block but misaligned + * and burst accesses cannot occur across the 0x20000000 boundary + * that separates the two SRAM arrays. Hence, treat the two arrays + * as separate memory ranges. + */ + sram_l: sram@1ffe0000 { + compatible = "mmio-sram"; + reg = <0x1ffe0000 DT_SIZE_K(128)>; + }; + + sram_u: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(124)>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; + +&ftfc { + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0 DT_SIZE_K(1536)>; + erase-block-size = ; + write-block-size = <8>; + }; +}; + +&lpuart2 { + clocks = <&clock NXP_S32_LPUART2_CLK>; +}; + +&lpspi1 { + clocks = <&clock NXP_S32_LPSPI1_CLK>; +}; + +&lpspi2 { + clocks = <&clock NXP_S32_LPSPI2_CLK>; +}; + +&flexcan0 { + interrupts = <78 0>, <79 0>, <80 0>, <81 0>, <82 0>; + interrupt-names = "warning", "error", "wake-up", "mb-0-15", "mb-16-31"; +}; + +&flexcan1 { + interrupts = <85 0>, <86 0>, <88 0>, <89 0>; + interrupt-names = "warning", "error", "mb-0-15", "mb-16-31"; + clocks = <&clock NXP_S32_FLEXCAN1_CLK>; +}; + +&flexcan2 { + interrupts = <92 0>, <93 0>, <95 0>, <96 0>; + interrupt-names = "warning", "error", "mb-0-15", "mb-16-31"; + clocks = <&clock NXP_S32_FLEXCAN2_CLK>; +}; diff --git a/include/zephyr/dt-bindings/clock/nxp_s32k148_clock.h b/include/zephyr/dt-bindings/clock/nxp_s32k148_clock.h new file mode 100644 index 00000000000..f50254977ac --- /dev/null +++ b/include/zephyr/dt-bindings/clock/nxp_s32k148_clock.h @@ -0,0 +1,100 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K148_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K148_CLOCK_H_ + +#define NXP_S32_LPO_128K_CLK 1U +#define NXP_S32_SIRC_CLK 2U +#define NXP_S32_SIRC_VLP_CLK 3U +#define NXP_S32_SIRC_STOP_CLK 4U +#define NXP_S32_FIRC_CLK 5U +#define NXP_S32_FIRC_VLP_CLK 6U +#define NXP_S32_FIRC_STOP_CLK 7U +#define NXP_S32_SOSC_CLK 8U +#define NXP_S32_SPLL_CLK 9U +#define NXP_S32_SIRCDIV1_CLK 10U +#define NXP_S32_SIRCDIV2_CLK 11U +#define NXP_S32_FIRCDIV1_CLK 12U +#define NXP_S32_FIRCDIV2_CLK 13U +#define NXP_S32_SOSCDIV1_CLK 14U +#define NXP_S32_SOSCDIV2_CLK 15U +#define NXP_S32_SPLLDIV1_CLK 16U +#define NXP_S32_SPLLDIV2_CLK 17U +#define NXP_S32_LPO_32K_CLK 18U +#define NXP_S32_LPO_1K_CLK 19U +#define NXP_S32_TCLK0_REF_CLK 20U +#define NXP_S32_TCLK1_REF_CLK 21U +#define NXP_S32_TCLK2_REF_CLK 22U +#define NXP_S32_SCS_CLK 24U +#define NXP_S32_SCS_RUN_CLK 25U +#define NXP_S32_SCS_VLPR_CLK 26U +#define NXP_S32_SCS_HSRUN_CLK 27U +#define NXP_S32_CORE_CLK 28U +#define NXP_S32_CORE_RUN_CLK 29U +#define NXP_S32_CORE_VLPR_CLK 30U +#define NXP_S32_CORE_HSRUN_CLK 31U +#define NXP_S32_BUS_CLK 32U +#define NXP_S32_BUS_RUN_CLK 33U +#define NXP_S32_BUS_VLPR_CLK 34U +#define NXP_S32_BUS_HSRUN_CLK 35U +#define NXP_S32_SLOW_CLK 36U +#define NXP_S32_SLOW_RUN_CLK 37U +#define NXP_S32_SLOW_VLPR_CLK 38U +#define NXP_S32_SLOW_HSRUN_CLK 39U +#define NXP_S32_RTC_CLK 40U +#define NXP_S32_LPO_CLK 41U +#define NXP_S32_SCG_CLKOUT_CLK 42U +#define NXP_S32_FTM0_EXT_CLK 43U +#define NXP_S32_FTM1_EXT_CLK 44U +#define NXP_S32_FTM2_EXT_CLK 45U +#define NXP_S32_FTM3_EXT_CLK 46U +#define NXP_S32_FTM4_EXT_CLK 47U +#define NXP_S32_FTM5_EXT_CLK 48U +#define NXP_S32_ADC0_CLK 50U +#define NXP_S32_ADC1_CLK 51U +#define NXP_S32_CLKOUT0_CLK 52U +#define NXP_S32_CMP0_CLK 53U +#define NXP_S32_CRC0_CLK 54U +#define NXP_S32_DMA0_CLK 55U +#define NXP_S32_DMAMUX0_CLK 56U +#define NXP_S32_EIM0_CLK 57U +#define NXP_S32_ENET_CLK 58U +#define NXP_S32_ERM0_CLK 59U +#define NXP_S32_EWM0_CLK 60U +#define NXP_S32_FLEXCAN0_CLK 61U +#define NXP_S32_FLEXCAN1_CLK 62U +#define NXP_S32_FLEXCAN2_CLK 63U +#define NXP_S32_FLEXIO_CLK 64U +#define NXP_S32_FTFC_CLK 65U +#define NXP_S32_FTM0_CLK 66U +#define NXP_S32_FTM1_CLK 67U +#define NXP_S32_FTM2_CLK 68U +#define NXP_S32_FTM3_CLK 69U +#define NXP_S32_FTM4_CLK 70U +#define NXP_S32_FTM5_CLK 71U +#define NXP_S32_LPI2C0_CLK 72U +#define NXP_S32_LPIT0_CLK 73U +#define NXP_S32_LPSPI0_CLK 74U +#define NXP_S32_LPSPI1_CLK 75U +#define NXP_S32_LPSPI2_CLK 76U +#define NXP_S32_LPTMR0_CLK 77U +#define NXP_S32_LPUART0_CLK 78U +#define NXP_S32_LPUART1_CLK 79U +#define NXP_S32_LPUART2_CLK 80U +#define NXP_S32_MPU0_CLK 81U +#define NXP_S32_MSCM0_CLK 82U +#define NXP_S32_PDB0_CLK 83U +#define NXP_S32_PDB1_CLK 84U +#define NXP_S32_PORTA_CLK 85U +#define NXP_S32_PORTB_CLK 86U +#define NXP_S32_PORTC_CLK 87U +#define NXP_S32_PORTD_CLK 88U +#define NXP_S32_PORTE_CLK 89U +#define NXP_S32_RTC0_CLK 90U +#define NXP_S32_TRACE_CLK 91U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K148_CLOCK_H_ */ diff --git a/samples/drivers/adc/adc_dt/boards/s32k148_evb.overlay b/samples/drivers/adc/adc_dt/boards/s32k148_evb.overlay new file mode 100644 index 00000000000..3ee980d0625 --- /dev/null +++ b/samples/drivers/adc/adc_dt/boards/s32k148_evb.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 Accenture + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + zephyr,user { + io-channels = <&adc0 28>; + }; +}; + +&pinctrl { + adc0_default: adc0_default { + group_1 { + pinmux = ; + drive-strength = "low"; + }; + }; +}; + +&adc0 { + #address-cells = <1>; + #size-cells = <0>; + + channel@1c { + reg = <28>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; diff --git a/samples/drivers/adc/adc_dt/sample.yaml b/samples/drivers/adc/adc_dt/sample.yaml index 1592685e9f7..3a844c71b6f 100644 --- a/samples/drivers/adc/adc_dt/sample.yaml +++ b/samples/drivers/adc/adc_dt/sample.yaml @@ -41,6 +41,7 @@ tests: - raytac_an54l15q_db/nrf54l15/cpuapp - frdm_mcxa166 - frdm_mcxa276 + - s32k148_evb integration_platforms: - nucleo_l073rz - nrf52840dk/nrf52840 diff --git a/samples/drivers/adc/adc_sequence/boards/s32k148_evb.overlay b/samples/drivers/adc/adc_sequence/boards/s32k148_evb.overlay new file mode 100644 index 00000000000..d17707f66fe --- /dev/null +++ b/samples/drivers/adc/adc_sequence/boards/s32k148_evb.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 Accenture + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + adc0 = &adc0; + }; +}; + +&pinctrl { + adc0_default: adc0_default { + group_1 { + pinmux = ; + drive-strength = "low"; + }; + }; +}; + +&adc0 { + #address-cells = <1>; + #size-cells = <0>; + + channel@1c { + reg = <28>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; diff --git a/samples/drivers/adc/adc_sequence/sample.yaml b/samples/drivers/adc/adc_sequence/sample.yaml index 9a824045d13..facedaf38d0 100644 --- a/samples/drivers/adc/adc_sequence/sample.yaml +++ b/samples/drivers/adc/adc_sequence/sample.yaml @@ -14,6 +14,7 @@ tests: - ophelia4ev/nrf54l15/cpuapp - raytac_an54l15q_db/nrf54l15/cpuapp - ucans32k1sic + - s32k148_evb - frdm_mcxc242 - stm32f3_disco integration_platforms: diff --git a/tests/drivers/adc/adc_api/boards/s32k148_evb.overlay b/tests/drivers/adc/adc_api/boards/s32k148_evb.overlay new file mode 100644 index 00000000000..d7f36527fcd --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/s32k148_evb.overlay @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Accenture + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + zephyr,user { + io-channels = <&adc0 28>; + }; +}; + +&pinctrl { + adc0_default: adc0_default { + group_1 { + pinmux = ; + drive-strength = "low"; + }; + }; +}; + +&adc0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + status = "okay"; + + channel@1c { + reg = <28>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&adc1 { + status = "disabled"; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/s32k148_evb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/s32k148_evb.overlay new file mode 100644 index 00000000000..6d94daf3b9f --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/s32k148_evb.overlay @@ -0,0 +1,13 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpioa 0 0>; + in-gpios = <&gpioa 1 0>; + }; +}; diff --git a/tests/drivers/gpio/gpio_hogs/boards/s32k148_evb.overlay b/tests/drivers/gpio/gpio_hogs/boards/s32k148_evb.overlay new file mode 100644 index 00000000000..7b4324fb920 --- /dev/null +++ b/tests/drivers/gpio/gpio_hogs/boards/s32k148_evb.overlay @@ -0,0 +1,35 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + zephyr,user { + output-high-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + output-low-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>; + input-gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpioa { + hog1 { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + }; + + hog2 { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + }; + + hog3 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; diff --git a/west.yml b/west.yml index 7a9aaaa3046..cc0b216a7d3 100644 --- a/west.yml +++ b/west.yml @@ -210,7 +210,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 02a29484f825f5315a45f46443446ce8c37a893d + revision: e8f6f6d8280fa589aa6ce36e6e7d4187597eaf54 path: modules/hal/nxp groups: - hal