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boards: arm: s32z270dc2_r52: enable CAN support

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Enable CAN instances on s32z270dc2_r52 boards

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
This commit is contained in:
Cong Nguyen Huu 2022-11-30 08:47:14 +07:00 committed by Carles Cufí
parent cad17ff933
commit 6559f2f2cf
7 changed files with 75 additions and 0 deletions
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22
boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi
View File

@ -52,4 +52,26 @@
output-enable;
};
};
can0_default: can0_default {
group1 {
pinmux = <PN2_CANXL_0_RX>;
input-enable;
};
group2 {
pinmux = <PN1_CANXL_0_TX>;
output-enable;
};
};
can1_default: can1_default {
group1 {
pinmux = <PM11_CANXL_1_RX>;
input-enable;
};
group2 {
pinmux = <PM10_CANXL_1_TX>;
output-enable;
};
};
};

25
boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi
View File

@ -112,3 +112,28 @@
phy-dev = <&phy0>;
status = "okay";
};
&can0 {
pinctrl-0 = <&can0_default>;
pinctrl-names = "default";
clock-frequency = <80000000>;
bus-speed = <125000>;
sample-point = <875>;
sjw = <1>;
bus-speed-data = <1000000>;
sample-point-data = <875>;
sjw-data = <1>;
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_default>;
pinctrl-names = "default";
clock-frequency = <80000000>;
bus-speed = <125000>;
sample-point = <875>;
sjw = <1>;
bus-speed-data = <1000000>;
sample-point-data = <875>;
sjw-data = <1>;
};

1
boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts
View File

@ -16,6 +16,7 @@
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,canbus = &can0;
};
aliases {

1
boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml
View File

@ -13,3 +13,4 @@ supported:
- gpio
- watchdog
- netif:eth
- can

1
boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts
View File

@ -16,6 +16,7 @@
zephyr,sram = &sram1;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,canbus = &can0;
};
aliases {

1
boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml
View File

@ -13,3 +13,4 @@ supported:
- gpio
- watchdog
- netif:eth
- can

24
dts/arm/nxp/nxp_s32z27x_r52.dtsi
View File

@ -658,5 +658,29 @@
status = "disabled";
};
};
can0: can@4741b000 {
compatible = "nxp,s32-canxl";
reg = <0x4741b000 0x4000>,
<0x47426000 0x4000>,
<0x47424000 0x4000>;
reg-names = "sic", "grp_ctrl", "dsc_ctrl";
status = "disabled";
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 225 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "RX_TX_DATA_IRQ", "INT_ERROR_IRQ";
};
can1: can@4751b000 {
compatible = "nxp,s32-canxl";
reg = <0x4751b000 0x4000>,
<0x47526000 0x4000>,
<0x47524000 0x4000>;
reg-names = "sic", "grp_ctrl", "dsc_ctrl";
status = "disabled";
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 227 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "RX_TX_DATA_IRQ", "INT_ERROR_IRQ";
};
};
};