From 627a3b83cdc128604202dfcb7cde324321906370 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 14 Jan 2025 15:12:21 +0800 Subject: [PATCH] arch: arm: cortex_m: handle multi-level interrupts in irq init Multi-level interrupts should be handled in irq init. Only level1 interrupts going directly to interrupt controller need to be initialized. Signed-off-by: Yangbo Lu --- arch/arm/core/cortex_m/irq_init.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/core/cortex_m/irq_init.c b/arch/arm/core/cortex_m/irq_init.c index b6b128e3368..edd1f519677 100644 --- a/arch/arm/core/cortex_m/irq_init.c +++ b/arch/arm/core/cortex_m/irq_init.c @@ -27,7 +27,12 @@ void z_arm_interrupt_init(void) { int irq = 0; +/* CONFIG_2ND_LVL_ISR_TBL_OFFSET could be treated as total number of level1 interrupts */ +#if defined(CONFIG_MULTI_LEVEL_INTERRUPTS) && defined(CONFIG_2ND_LVL_ISR_TBL_OFFSET) + for (; irq < CONFIG_2ND_LVL_ISR_TBL_OFFSET; irq++) { +#else for (; irq < CONFIG_NUM_IRQS; irq++) { +#endif NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET); } }