From 618044ed78158f18fbb1452952eff9862de473af Mon Sep 17 00:00:00 2001 From: Khaoula Bidani Date: Tue, 1 Jul 2025 14:09:15 +0200 Subject: [PATCH] drivers: clock_control: fix PLL input frequency Correct PLL input frequency calculation to consider HSI clock divider in clock_stm32_ll_h7.c file. For sake of simplicity, use PLLSRC_FREQmacro that already considers the HSI clock divider when applicable. Signed-off-by: Khaoula Bidani --- drivers/clock_control/clock_stm32_ll_h7.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 4252fbc3b62..42977c65a50 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -217,17 +217,12 @@ static uint32_t get_pllout_frequency(uint32_t pllsrc_freq, __unused static uint32_t get_pllsrc_frequency(void) { - switch (LL_RCC_PLL_GetSource()) { - case LL_RCC_PLLSOURCE_HSI: - return STM32_HSI_FREQ; - case LL_RCC_PLLSOURCE_CSI: - return STM32_CSI_FREQ; - case LL_RCC_PLLSOURCE_HSE: - return STM32_HSE_FREQ; - case LL_RCC_PLLSOURCE_NONE: - default: - return 0; - } +/* M4 is not expected to call this function */ +#ifdef CONFIG_CPU_CORTEX_M7 + return PLLSRC_FREQ; +#else + return 0; +#endif } __unused