diff --git a/drivers/flash/nrf_qspi_nor.c b/drivers/flash/nrf_qspi_nor.c
index ca49240e192..691360a9b8e 100644
--- a/drivers/flash/nrf_qspi_nor.c
+++ b/drivers/flash/nrf_qspi_nor.c
@@ -180,6 +180,10 @@ struct qspi_cmd {
 static int qspi_nor_write_protection_set(const struct device *dev,
 					 bool write_protect);
 
+#ifdef CONFIG_PM_DEVICE
+static int exit_dpd(const struct device *const dev);
+#endif
+
 /**
  * @brief Test whether offset is aligned.
  */
@@ -580,6 +584,19 @@ static int qspi_nrfx_configure(const struct device *dev)
 	}
 #endif
 
+#ifdef CONFIG_PM_DEVICE
+	/* It may happen that after the flash chip was previously put into
+	 * the DPD mode, the system was reset but the flash chip was not.
+	 * Consequently, the flash chip can be in the DPD mode at this point.
+	 * Some flash chips will just exit the DPD mode on the first CS pulse,
+	 * but some need to receive the dedicated command to do it, so send it.
+	 */
+	ret = exit_dpd(dev);
+	if (ret < 0) {
+		return ret;
+	}
+#endif
+
 	if (INST_0_QER != JESD216_DW15_QER_NONE) {
 		/* Set QE to match transfer mode.  If not using quad
 		 * it's OK to leave QE set, but doing so prevents use