From 5efea4283c3fade269e7fa09d5becdddf8fc780e Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 25 Jun 2021 21:58:10 +0100 Subject: [PATCH] drivers: flash: stm32f4: Flush caches after erase This implement the same flush cache functionality already present in the other stm32 series flash drivers, used to avoid bus errors when writing big chunks of data to the flash. Signed-off-by: Fabio Baltieri --- drivers/flash/flash_stm32l4x.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/flash/flash_stm32l4x.c b/drivers/flash/flash_stm32l4x.c index a77e0715e7a..fde5a7296c7 100644 --- a/drivers/flash/flash_stm32l4x.c +++ b/drivers/flash/flash_stm32l4x.c @@ -40,6 +40,30 @@ bool flash_stm32_valid_range(const struct device *dev, off_t offset, flash_stm32_range_exists(dev, offset, len); } +static inline void flush_cache(FLASH_TypeDef *regs) +{ + if (regs->ACR & FLASH_ACR_DCEN) { + regs->ACR &= ~FLASH_ACR_DCEN; + /* Datasheet: DCRST: Data cache reset + * This bit can be written only when thes data cache is disabled + */ + regs->ACR |= FLASH_ACR_DCRST; + regs->ACR &= ~FLASH_ACR_DCRST; + regs->ACR |= FLASH_ACR_DCEN; + } + + if (regs->ACR & FLASH_ACR_ICEN) { + regs->ACR &= ~FLASH_ACR_ICEN; + /* Datasheet: ICRST: Instruction cache reset : + * This bit can be written only when the instruction cache + * is disabled + */ + regs->ACR |= FLASH_ACR_ICRST; + regs->ACR &= ~FLASH_ACR_ICRST; + regs->ACR |= FLASH_ACR_ICEN; + } +} + /* * STM32L4xx devices can have up to 512 2K pages on two 256x2K pages banks * @@ -163,6 +187,8 @@ static int erase_page(const struct device *dev, unsigned int page) return rc; } + flush_cache(regs); + /* Set the PER bit and select the page you wish to erase */ regs->CR |= FLASH_CR_PER; #ifdef FLASH_CR_BKER