Bluetooth: Controller: nordic: Rework hw resources files
Move all defines that specifies (D)PPI resources which are used to dedicated files which have no include dependencies. This allow to use them in nrfx_glue.h to specify fixed (D)PPI channels used by the bluetooth. Additionally, added mask with GPIOTE channels used by the bluetooth controller. It was previously not defined which could lead to conflicts since same channels could be allocated by the nrfx_gpiote user Updated nrfx_glue.h to use new approach. Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit is contained in:
Krzysztof Chruscinski
Carles Cufí
parent
1345b2ddd4
commit
5ef63d8313
@ -272,39 +272,58 @@ void nrfx_busy_wait(uint32_t usec_to_wait);
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NRFX_PPI_GROUPS_USED_BY_MPSL)
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/** @brief Bitmask that defines GPIOTE channels that are reserved for use outside of the nrfx library. */
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#define NRFX_GPIOTE_CHANNELS_USED 0
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#define NRFX_GPIOTE_CHANNELS_USED NRFX_GPIOTE_CHANNELS_USED_BY_BT_CTLR
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#if defined(CONFIG_BT_CTLR)
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extern const uint32_t z_bt_ctlr_used_nrf_ppi_channels;
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extern const uint32_t z_bt_ctlr_used_nrf_ppi_groups;
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#define NRFX_PPI_CHANNELS_USED_BY_BT_CTLR z_bt_ctlr_used_nrf_ppi_channels
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#define NRFX_PPI_GROUPS_USED_BY_BT_CTLR z_bt_ctlr_used_nrf_ppi_groups
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#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_resources.h>
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#define NRFX_PPI_CHANNELS_USED_BY_BT_CTLR BT_CTLR_USED_PPI_CHANNELS
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#define NRFX_PPI_GROUPS_USED_BY_BT_CTLR BT_CTLR_USED_PPI_GROUPS
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#define NRFX_GPIOTE_CHANNELS_USED_BY_BT_CTLR BT_CTLR_USED_GPIOTE_CHANNELS
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#else
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#define NRFX_PPI_CHANNELS_USED_BY_BT_CTLR 0
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#define NRFX_PPI_GROUPS_USED_BY_BT_CTLR 0
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#define NRFX_PPI_CHANNELS_USED_BY_BT_CTLR 0
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#define NRFX_PPI_GROUPS_USED_BY_BT_CTLR 0
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#define NRFX_GPIOTE_CHANNELS_USED_BY_BT_CTLR 0
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#endif
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#if defined(CONFIG_NRF_802154_RADIO_DRIVER)
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extern const uint32_t g_nrf_802154_used_nrf_ppi_channels;
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extern const uint32_t g_nrf_802154_used_nrf_ppi_groups;
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#define NRFX_PPI_CHANNELS_USED_BY_802154_DRV g_nrf_802154_used_nrf_ppi_channels
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#define NRFX_PPI_GROUPS_USED_BY_802154_DRV g_nrf_802154_used_nrf_ppi_groups
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#if defined(NRF52_SERIES)
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#include <../src/nrf_802154_peripherals_nrf52.h>
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#define NRFX_PPI_CHANNELS_USED_BY_802154_DRV NRF_802154_PPI_CHANNELS_USED_MASK
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#define NRFX_PPI_GROUPS_USED_BY_802154_DRV NRF_802154_PPI_GROUPS_USED_MASK
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#elif defined(NRF53_SERIES)
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#include <../src/nrf_802154_peripherals_nrf53.h>
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#define NRFX_PPI_CHANNELS_USED_BY_802154_DRV NRF_802154_DPPI_CHANNELS_USED_MASK
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#define NRFX_PPI_GROUPS_USED_BY_802154_DRV NRF_802154_DPPI_GROUPS_USED_MASK
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#else
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#error Unsupported chip family
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#endif
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#else // CONFIG_NRF_802154_RADIO_DRIVER
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#define NRFX_PPI_CHANNELS_USED_BY_802154_DRV 0
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#define NRFX_PPI_GROUPS_USED_BY_802154_DRV 0
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#endif
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#endif // CONFIG_NRF_802154_RADIO_DRIVER
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#if defined(CONFIG_NRF_802154_RADIO_DRIVER) && \
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!defined(CONFIG_NRF_802154_SL_OPENSOURCE)
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extern const uint32_t z_mpsl_used_nrf_ppi_channels;
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extern const uint32_t z_mpsl_used_nrf_ppi_groups;
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#define NRFX_PPI_CHANNELS_USED_BY_MPSL z_mpsl_used_nrf_ppi_channels
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#define NRFX_PPI_GROUPS_USED_BY_MPSL z_mpsl_used_nrf_ppi_groups
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#if defined(CONFIG_NRF_802154_RADIO_DRIVER) && !defined(CONFIG_NRF_802154_SL_OPENSOURCE)
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#include <mpsl.h>
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#define NRFX_PPI_CHANNELS_USED_BY_MPSL MPSL_RESERVED_PPI_CHANNELS
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#define NRFX_PPI_GROUPS_USED_BY_MPSL 0
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#else
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#define NRFX_PPI_CHANNELS_USED_BY_MPSL 0
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#define NRFX_PPI_GROUPS_USED_BY_MPSL 0
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#endif
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#if NRF_802154_VERIFY_PERIPHS_ALLOC_AGAINST_MPSL
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BUILD_ASSERT(
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(NRFX_PPI_CHANNELS_USED_BY_802154_DRV & NRFX_PPI_CHANNELS_USED_BY_MPSL) == 0,
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"PPI channels used by the IEEE802.15.4 radio driver overlap with those "
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"assigned to the MPSL.");
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BUILD_ASSERT(
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(NRFX_PPI_GROUPS_USED_BY_802154_DRV & NRFX_PPI_GROUPS_USED_BY_MPSL) == 0,
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"PPI groups used by the IEEE802.15.4 radio driver overlap with those "
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"assigned to the MPSL.");
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#endif // NRF_802154_VERIFY_PERIPHS_ALLOC_AGAINST_MPSL
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/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */
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#define NRFX_EGUS_USED 0
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@ -122,12 +122,6 @@ BUILD_ASSERT(DT_NODE_HAS_COMPAT(NRF_GPIO_CSN_CTLR, nordic_nrf_gpio),
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#endif /* HAL_RADIO_FEM_IS_NRF21540 */
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/* The following two constants are used in nrfx_glue.h for marking these PPI
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* channels and groups as occupied and thus unavailable to other modules.
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*/
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const uint32_t z_bt_ctlr_used_nrf_ppi_channels = HAL_USED_PPI_CHANNELS;
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const uint32_t z_bt_ctlr_used_nrf_ppi_groups = HAL_USED_PPI_GROUPS;
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static radio_isr_cb_t isr_cb;
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static void *isr_cb_param;
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@ -50,10 +50,6 @@
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#include <nrf_peripherals.h>
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#define HAL_PALNA_GPIOTE_CHAN 0
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#define HAL_PDN_GPIOTE_CHAN 1
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#define HAL_CSN_GPIOTE_CHAN 2
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/* This has to come before the ppi/dppi includes below. */
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#include "radio_nrf5_fem.h"
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@ -8,7 +8,6 @@
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#if !defined(CONFIG_BT_CTLR_TIFS_HW)
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#define SW_SWITCH_TIMER NRF_TIMER1
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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/* TXEN->TXIDLE + TXIDLE->TX in microseconds. */
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@ -190,7 +190,6 @@
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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static inline void hal_radio_reset(void)
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@ -189,8 +189,6 @@
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#define SW_SWITCH_TIMER NRF_TIMER1
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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static inline void hal_radio_reset(void)
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@ -353,8 +353,6 @@
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#define SW_SWITCH_TIMER_EVTS_COMP_S2_BASE 2
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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static inline void hal_radio_reset(void)
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@ -353,8 +353,6 @@
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#define SW_SWITCH_TIMER_EVTS_COMP_S2_BASE 2
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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static inline void hal_radio_reset(void)
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@ -190,8 +190,6 @@
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#define SW_SWITCH_TIMER NRF_TIMER1
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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static inline void hal_radio_reset(void)
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@ -353,8 +353,6 @@
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#define SW_SWITCH_TIMER_EVTS_COMP_S2_BASE 2
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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static inline void hal_radio_reset(void)
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@ -354,8 +354,6 @@
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#define SW_SWITCH_TIMER_EVTS_COMP_S2_BASE 2
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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static inline void hal_radio_reset(void)
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@ -354,8 +354,6 @@
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
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#define SW_SWITCH_TIMER_EVTS_COMP_S2_BASE 2
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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static inline void hal_radio_reset(void)
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@ -4,7 +4,6 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#if defined(CONFIG_SOC_NRF5340_CPUNET) || defined(DPPI_PRESENT)
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#include <hal/nrf_dppi.h>
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@ -15,6 +14,8 @@
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#include <hal/nrf_aar.h>
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#include <hal/nrf_gpiote.h>
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#include "radio_nrf5_dppi_resources.h"
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static inline void hal_radio_nrf_ppi_channels_enable(uint32_t mask)
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{
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nrf_dppi_channels_enable(NRF_DPPIC, mask);
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@ -29,10 +30,6 @@ static inline void hal_radio_nrf_ppi_channels_disable(uint32_t mask)
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* Enable Radio on Event Timer tick:
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* wire the EVENT_TIMER EVENTS_COMPARE[0] event to RADIO TASKS_TXEN/RXEN task.
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*/
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#define HAL_RADIO_ENABLE_ON_TICK_PPI 6
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#define HAL_RADIO_ENABLE_TX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
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#define HAL_RADIO_ENABLE_RX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
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static inline void hal_radio_enable_on_tick_ppi_config_and_enable(uint8_t trx)
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{
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nrf_timer_publish_set(EVENT_TIMER, NRF_TIMER_EVENT_COMPARE0, HAL_RADIO_ENABLE_ON_TICK_PPI);
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@ -63,8 +60,6 @@ static inline void hal_radio_enable_on_tick_ppi_config_and_enable(uint8_t trx)
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* wire the RADIO EVENTS_ADDRESS event to the
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* EVENT_TIMER TASKS_CAPTURE[<address timer>] task.
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*/
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#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 9
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static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
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{
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nrf_radio_publish_set(NRF_RADIO,
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@ -78,8 +73,6 @@ static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
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* wire the EVENT_TIMER EVENTS_COMPARE[<HCTO timer>] event
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* to the RADIO TASKS_DISABLE task.
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*/
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#define HAL_RADIO_DISABLE_ON_HCTO_PPI 10
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static inline void hal_radio_disable_on_hcto_ppi_config(void)
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{
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nrf_timer_publish_set(EVENT_TIMER,
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@ -93,8 +86,6 @@ static inline void hal_radio_disable_on_hcto_ppi_config(void)
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* wire the RADIO EVENTS_END event to the
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* EVENT_TIMER TASKS_CAPTURE[<radio end timer>] task.
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*/
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#define HAL_RADIO_END_TIME_CAPTURE_PPI 11
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static inline void hal_radio_end_time_capture_ppi_config(void)
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{
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nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_END, HAL_RADIO_END_TIME_CAPTURE_PPI);
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@ -106,8 +97,6 @@ static inline void hal_radio_end_time_capture_ppi_config(void)
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* Start event timer on RTC tick:
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* wire the RTC0 EVENTS_COMPARE[2] event to EVENT_TIMER TASKS_START task.
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*/
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#define HAL_EVENT_TIMER_START_PPI 7
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static inline void hal_event_timer_start_ppi_config(void)
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{
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nrf_rtc_publish_set(NRF_RTC0, NRF_RTC_EVENT_COMPARE_2, HAL_EVENT_TIMER_START_PPI);
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@ -119,8 +108,6 @@ static inline void hal_event_timer_start_ppi_config(void)
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* wire the RADIO EVENTS_READY event to the
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* EVENT_TIMER TASKS_CAPTURE[<radio ready timer>] task.
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*/
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#define HAL_RADIO_READY_TIME_CAPTURE_PPI 8
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static inline void hal_radio_ready_time_capture_ppi_config(void)
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{
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nrf_radio_publish_set(NRF_RADIO,
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@ -136,8 +123,6 @@ static inline void hal_radio_ready_time_capture_ppi_config(void)
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* Note: we do not need an additional PPI, since we have already set up
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* a PPI to publish RADIO ADDRESS event.
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*/
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#define HAL_TRIGGER_CRYPT_PPI HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI
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static inline void hal_trigger_crypt_ppi_config(void)
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{
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nrf_radio_publish_set(NRF_RADIO,
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@ -149,8 +134,6 @@ static inline void hal_trigger_crypt_ppi_config(void)
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* Trigger automatic address resolution on Bit counter match:
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* wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task.
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*/
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#define HAL_TRIGGER_AAR_PPI 12
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static inline void hal_trigger_aar_ppi_config(void)
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{
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nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_BCMATCH, HAL_TRIGGER_AAR_PPI);
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@ -160,8 +143,6 @@ static inline void hal_trigger_aar_ppi_config(void)
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/*******************************************************************************
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* Trigger Radio Rate override upon Rateboost event.
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*/
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#define HAL_TRIGGER_RATEOVERRIDE_PPI 13
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static inline void hal_trigger_rateoverride_ppi_config(void)
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{
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nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_RATEBOOST, HAL_TRIGGER_RATEOVERRIDE_PPI);
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@ -169,14 +150,7 @@ static inline void hal_trigger_rateoverride_ppi_config(void)
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}
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/******************************************************************************/
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#define HAL_ENABLE_PALNA_PPI 5
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#if defined(HAL_RADIO_FEM_IS_NRF21540)
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#define HAL_DISABLE_PALNA_PPI 4
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#else
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#define HAL_DISABLE_PALNA_PPI HAL_ENABLE_PALNA_PPI
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#endif
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#if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
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static inline void hal_palna_ppi_setup(void)
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{
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nrf_timer_publish_set(EVENT_TIMER, NRF_TIMER_EVENT_COMPARE2,
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@ -191,6 +165,7 @@ static inline void hal_palna_ppi_setup(void)
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nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
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#endif
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}
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#endif /* defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN) */
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/******************************************************************************/
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#if defined(HAL_RADIO_FEM_IS_NRF21540)
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@ -229,9 +204,6 @@ static inline void hal_lna_ppi_setup(void)
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#endif /* !HAL_RADIO_GPIO_LNA_POL_INV */
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}
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#define HAL_ENABLE_FEM_PPI 3
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#define HAL_DISABLE_FEM_PPI HAL_DISABLE_PALNA_PPI
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static inline void hal_fem_ppi_setup(void)
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{
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nrf_gpiote_task_t task;
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@ -278,8 +250,6 @@ static inline void hal_fem_ppi_setup(void)
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* Note: we do not need an additional PPI, since we have already set up
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* a PPI to publish RADIO END event.
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*/
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#define HAL_SW_SWITCH_TIMER_CLEAR_PPI HAL_RADIO_END_TIME_CAPTURE_PPI
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static inline void hal_sw_switch_timer_clear_ppi_config(void)
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{
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nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_END, HAL_SW_SWITCH_TIMER_CLEAR_PPI);
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@ -318,7 +288,6 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
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* 2 adjacent PPIs (8 & 9) and 2 adjacent PPI groups are used for this wiring;
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* <index> must be 0 or 1. <offset> must be a valid TIMER CC register offset.
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*/
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#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 14
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#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(index) \
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(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE + (index))
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@ -343,7 +312,6 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
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* Note: we do not need an additional PPI, since we have already set up
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* a PPI to publish RADIO END event.
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*/
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#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI HAL_SW_SWITCH_TIMER_CLEAR_PPI
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#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_EVT \
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(NRF_RADIO->PUBLISH_END)
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#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT \
|
||||
@ -373,12 +341,9 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
* We use the same PPI for the alternative SW Switch Timer compare
|
||||
* event.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 14
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI(index) \
|
||||
(HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE + (index))
|
||||
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE \
|
||||
HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(index) \
|
||||
(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE + (index))
|
||||
|
||||
@ -410,7 +375,6 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
*
|
||||
* Note: We already have a PPI where we publish the RATEBOOST event.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI HAL_TRIGGER_RATEOVERRIDE_PPI
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT \
|
||||
NRF_RADIO->PUBLISH_RATEBOOST
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT \
|
||||
@ -630,71 +594,3 @@ static inline void hal_radio_group_task_disable_ppi_setup(void)
|
||||
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
|
||||
|
||||
#endif /* CONFIG_SOC_NRF5340_CPUNET || DPPI_PRESENT */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define HAL_USED_PPI_CHANNELS \
|
||||
(BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) | \
|
||||
BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) | \
|
||||
BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) | \
|
||||
BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) | \
|
||||
BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) | \
|
||||
BIT(HAL_EVENT_TIMER_START_PPI) | \
|
||||
BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) | \
|
||||
BIT(HAL_TRIGGER_CRYPT_PPI) | \
|
||||
BIT(HAL_TRIGGER_AAR_PPI) | \
|
||||
HAL_USED_PPI_CHANNELS_2 | HAL_USED_PPI_CHANNELS_3 | \
|
||||
HAL_USED_PPI_CHANNELS_4 | HAL_USED_PPI_CHANNELS_5 | \
|
||||
HAL_USED_PPI_CHANNELS_6)
|
||||
|
||||
#if defined(HAL_TRIGGER_RATEOVERRIDE_PPI)
|
||||
#define HAL_USED_PPI_CHANNELS_2 \
|
||||
BIT(HAL_TRIGGER_RATEOVERRIDE_PPI)
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_2 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_ENABLE_PALNA_PPI)
|
||||
#define HAL_USED_PPI_CHANNELS_3 \
|
||||
(BIT(HAL_ENABLE_PALNA_PPI) | \
|
||||
BIT(HAL_DISABLE_PALNA_PPI))
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_3 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_SW_SWITCH_TIMER_CLEAR_PPI)
|
||||
#define HAL_USED_PPI_CHANNELS_4 \
|
||||
(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE + 1) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE + 1))
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_4 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE)
|
||||
#define HAL_USED_PPI_CHANNELS_5 \
|
||||
(BIT(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE + 1) | \
|
||||
BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI))
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_5 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_ENABLE_FEM_PPI)
|
||||
#define HAL_USED_PPI_CHANNELS_6 \
|
||||
(BIT(HAL_ENABLE_FEM_PPI) | \
|
||||
BIT(HAL_DISABLE_FEM_PPI))
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_6 0
|
||||
#endif
|
||||
|
||||
#if defined(SW_SWITCH_TIMER_TASK_GROUP_BASE)
|
||||
#define HAL_USED_PPI_GROUPS \
|
||||
(BIT(SW_SWITCH_TIMER_TASK_GROUP_BASE) | \
|
||||
BIT(SW_SWITCH_TIMER_TASK_GROUP_BASE + 1))
|
||||
#else
|
||||
#define HAL_USED_PPI_GROUPS 0
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#if defined(CONFIG_SOC_NRF5340_CPUNET) || defined(DPPI_PRESENT)
|
||||
|
||||
/*******************************************************************************
|
||||
* Enable Radio on Event Timer tick:
|
||||
* wire the EVENT_TIMER EVENTS_COMPARE[0] event to RADIO TASKS_TXEN/RXEN task.
|
||||
*/
|
||||
#define HAL_RADIO_ENABLE_ON_TICK_PPI 6
|
||||
#define HAL_RADIO_ENABLE_TX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
|
||||
#define HAL_RADIO_ENABLE_RX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
|
||||
|
||||
/*******************************************************************************
|
||||
* Capture event timer on Address reception:
|
||||
* wire the RADIO EVENTS_ADDRESS event to the
|
||||
* EVENT_TIMER TASKS_CAPTURE[<address timer>] task.
|
||||
*/
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 9
|
||||
|
||||
/*******************************************************************************
|
||||
* Disable Radio on HCTO:
|
||||
* wire the EVENT_TIMER EVENTS_COMPARE[<HCTO timer>] event
|
||||
* to the RADIO TASKS_DISABLE task.
|
||||
*/
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI 10
|
||||
|
||||
/*******************************************************************************
|
||||
* Capture event timer on Radio end:
|
||||
* wire the RADIO EVENTS_END event to the
|
||||
* EVENT_TIMER TASKS_CAPTURE[<radio end timer>] task.
|
||||
*/
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI 11
|
||||
|
||||
/*******************************************************************************
|
||||
* Start event timer on RTC tick:
|
||||
* wire the RTC0 EVENTS_COMPARE[2] event to EVENT_TIMER TASKS_START task.
|
||||
*/
|
||||
#define HAL_EVENT_TIMER_START_PPI 7
|
||||
|
||||
/*******************************************************************************
|
||||
* Capture event timer on Radio ready:
|
||||
* wire the RADIO EVENTS_READY event to the
|
||||
* EVENT_TIMER TASKS_CAPTURE[<radio ready timer>] task.
|
||||
*/
|
||||
#define HAL_RADIO_READY_TIME_CAPTURE_PPI 8
|
||||
|
||||
/*******************************************************************************
|
||||
* Trigger encryption task upon address reception:
|
||||
* wire the RADIO EVENTS_ADDRESS event to the CCM TASKS_CRYPT task.
|
||||
*
|
||||
* Note: we do not need an additional PPI, since we have already set up
|
||||
* a PPI to publish RADIO ADDRESS event.
|
||||
*/
|
||||
#define HAL_TRIGGER_CRYPT_PPI HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI
|
||||
|
||||
/*******************************************************************************
|
||||
* Trigger automatic address resolution on Bit counter match:
|
||||
* wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task.
|
||||
*/
|
||||
#define HAL_TRIGGER_AAR_PPI 12
|
||||
|
||||
/*******************************************************************************
|
||||
* Trigger Radio Rate override upon Rateboost event.
|
||||
*/
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI 13
|
||||
|
||||
/******************************************************************************/
|
||||
#define HAL_ENABLE_PALNA_PPI 5
|
||||
|
||||
#if defined(HAL_RADIO_FEM_IS_NRF21540)
|
||||
#define HAL_DISABLE_PALNA_PPI 4
|
||||
#else
|
||||
#define HAL_DISABLE_PALNA_PPI HAL_ENABLE_PALNA_PPI
|
||||
#endif
|
||||
|
||||
#define HAL_ENABLE_FEM_PPI 3
|
||||
#define HAL_DISABLE_FEM_PPI HAL_DISABLE_PALNA_PPI
|
||||
|
||||
/******************************************************************************/
|
||||
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
|
||||
/* DPPI setup used for SW-based auto-switching during TIFS. */
|
||||
|
||||
/* Clear SW-switch timer on packet end:
|
||||
* wire the RADIO EVENTS_END event to SW_SWITCH_TIMER TASKS_CLEAR task.
|
||||
*
|
||||
* Note: we do not need an additional PPI, since we have already set up
|
||||
* a PPI to publish RADIO END event.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI HAL_RADIO_END_TIME_CAPTURE_PPI
|
||||
|
||||
/* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
|
||||
* to a PPI GROUP TASK DISABLE task (PPI group with index <index>).
|
||||
* 2 adjacent PPIs (8 & 9) and 2 adjacent PPI groups are used for this wiring;
|
||||
* <index> must be 0 or 1. <offset> must be a valid TIMER CC register offset.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 14
|
||||
|
||||
/* Enable the SW Switch PPI Group on RADIO END Event.
|
||||
*
|
||||
* Note: we do not need an additional PPI, since we have already set up
|
||||
* a PPI to publish RADIO END event.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI HAL_SW_SWITCH_TIMER_CLEAR_PPI
|
||||
|
||||
/* Enable Radio on SW Switch timer event.
|
||||
* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
|
||||
* to a RADIO Enable task (TX or RX).
|
||||
*
|
||||
* Note:
|
||||
* We use the same PPI as for disabling the SW Switch PPI groups,
|
||||
* since we need to listen for the same event (SW Switch event).
|
||||
*
|
||||
* We use the same PPI for the alternative SW Switch Timer compare
|
||||
* event.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 14
|
||||
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE \
|
||||
HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE
|
||||
|
||||
/* Cancel the SW switch timer running considering S8 timing:
|
||||
* wire the RADIO EVENTS_RATEBOOST event to SW_SWITCH_TIMER TASKS_CAPTURE task.
|
||||
*
|
||||
* Note: We already have a PPI where we publish the RATEBOOST event.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI HAL_TRIGGER_RATEOVERRIDE_PPI
|
||||
|
||||
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
|
||||
|
||||
#endif /* CONFIG_SOC_NRF5340_CPUNET || DPPI_PRESENT */
|
||||
@ -4,11 +4,12 @@
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_COMPATIBLE_NRF52X)
|
||||
|
||||
#include <hal/nrf_ppi.h>
|
||||
|
||||
#include "radio_nrf5_ppi_resources.h"
|
||||
|
||||
static inline void hal_radio_nrf_ppi_channels_enable(uint32_t mask)
|
||||
{
|
||||
nrf_ppi_channels_enable(NRF_PPI, mask);
|
||||
@ -28,17 +29,6 @@ static inline void hal_radio_nrf_ppi_channels_disable(uint32_t mask)
|
||||
*/
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
|
||||
/* PPI channel 20 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[0]
|
||||
* TEP: RADIO->TASKS_TXEN
|
||||
*/
|
||||
#define HAL_RADIO_ENABLE_TX_ON_TICK_PPI 20
|
||||
/* PPI channel 21 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[0]
|
||||
* TEP: RADIO->TASKS_RXEN
|
||||
*/
|
||||
#define HAL_RADIO_ENABLE_RX_ON_TICK_PPI 21
|
||||
|
||||
static inline void hal_radio_enable_on_tick_ppi_config_and_enable(uint8_t trx)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channels.
|
||||
@ -56,10 +46,6 @@ static inline void hal_radio_enable_on_tick_ppi_config_and_enable(uint8_t trx)
|
||||
|
||||
#else
|
||||
|
||||
#define HAL_RADIO_ENABLE_ON_TICK_PPI 2
|
||||
#define HAL_RADIO_ENABLE_TX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
|
||||
#define HAL_RADIO_ENABLE_RX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
|
||||
|
||||
static inline void hal_radio_enable_on_tick_ppi_config_and_enable(uint8_t trx)
|
||||
{
|
||||
uint32_t event_address = (trx ? (uint32_t)&(NRF_RADIO->TASKS_TXEN)
|
||||
@ -84,12 +70,6 @@ static inline void hal_radio_enable_on_tick_ppi_config_and_enable(uint8_t trx)
|
||||
*/
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
|
||||
/* PPI channel 26 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_ADDRESS
|
||||
* TEP: TIMER0->TASKS_CAPTURE[1]
|
||||
*/
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 26
|
||||
|
||||
static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
@ -97,8 +77,6 @@ static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
|
||||
|
||||
#else
|
||||
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 3
|
||||
|
||||
static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
@ -120,12 +98,6 @@ static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
|
||||
*/
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
|
||||
/* PPI channel 22 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[1]
|
||||
* TEP: RADIO->TASKS_DISABLE
|
||||
*/
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI 22
|
||||
|
||||
static inline void hal_radio_disable_on_hcto_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
@ -133,8 +105,6 @@ static inline void hal_radio_disable_on_hcto_ppi_config(void)
|
||||
|
||||
#else
|
||||
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI 4
|
||||
|
||||
static inline void hal_radio_disable_on_hcto_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
@ -156,12 +126,6 @@ static inline void hal_radio_disable_on_hcto_ppi_config(void)
|
||||
*/
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
|
||||
/* PPI channel 27 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_END
|
||||
* TEP: TIMER0->TASKS_CAPTURE[2]
|
||||
*/
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI 27
|
||||
|
||||
static inline void hal_radio_end_time_capture_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
@ -169,8 +133,6 @@ static inline void hal_radio_end_time_capture_ppi_config(void)
|
||||
|
||||
#else
|
||||
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI 5
|
||||
|
||||
static inline void hal_radio_end_time_capture_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
@ -186,8 +148,6 @@ static inline void hal_radio_end_time_capture_ppi_config(void)
|
||||
* Start event timer on RTC tick:
|
||||
* wire the RTC0 EVENTS_COMPARE[2] event to EVENT_TIMER TASKS_START task.
|
||||
*/
|
||||
#define HAL_EVENT_TIMER_START_PPI 6
|
||||
|
||||
static inline void hal_event_timer_start_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
@ -202,8 +162,6 @@ static inline void hal_event_timer_start_ppi_config(void)
|
||||
* wire the RADIO EVENTS_READY event to the
|
||||
* EVENT_TIMER TASKS_CAPTURE[<radio ready timer>] task.
|
||||
*/
|
||||
#define HAL_RADIO_READY_TIME_CAPTURE_PPI 7
|
||||
|
||||
static inline void hal_radio_ready_time_capture_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
@ -221,8 +179,6 @@ static inline void hal_radio_ready_time_capture_ppi_config(void)
|
||||
* EEP: RADIO->EVENTS_ADDRESS
|
||||
* TEP: CCM->TASKS_CRYPT
|
||||
*/
|
||||
#define HAL_TRIGGER_CRYPT_PPI 25
|
||||
|
||||
static inline void hal_trigger_crypt_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
@ -236,8 +192,6 @@ static inline void hal_trigger_crypt_ppi_config(void)
|
||||
* EEP: RADIO->EVENTS_BCMATCH
|
||||
* TEP: AAR->TASKS_START
|
||||
*/
|
||||
#define HAL_TRIGGER_AAR_PPI 23
|
||||
|
||||
static inline void hal_trigger_aar_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
@ -247,9 +201,6 @@ static inline void hal_trigger_aar_ppi_config(void)
|
||||
* Trigger Radio Rate override upon Rateboost event.
|
||||
*/
|
||||
#if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
|
||||
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI 14
|
||||
|
||||
static inline void hal_trigger_rateoverride_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
@ -258,13 +209,10 @@ static inline void hal_trigger_rateoverride_ppi_config(void)
|
||||
(uint32_t)&(NRF_RADIO->EVENTS_RATEBOOST),
|
||||
(uint32_t)&(NRF_CCM->TASKS_RATEOVERRIDE));
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
|
||||
|
||||
/******************************************************************************/
|
||||
#define HAL_ENABLE_PALNA_PPI 15
|
||||
#define HAL_DISABLE_PALNA_PPI 16
|
||||
|
||||
#if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
|
||||
static inline void hal_palna_ppi_setup(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
@ -278,6 +226,7 @@ static inline void hal_palna_ppi_setup(void)
|
||||
(uint32_t)&(NRF_RADIO->EVENTS_DISABLED),
|
||||
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[HAL_PALNA_GPIOTE_CHAN]));
|
||||
}
|
||||
#endif /* defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN) */
|
||||
|
||||
/******************************************************************************/
|
||||
#if defined(HAL_RADIO_FEM_IS_NRF21540)
|
||||
@ -291,9 +240,6 @@ static inline void hal_lna_ppi_setup(void)
|
||||
/* Nothing specific to LNA with FEM to handle inside TRX chains */
|
||||
}
|
||||
|
||||
#define HAL_ENABLE_FEM_PPI 4
|
||||
#define HAL_DISABLE_FEM_PPI 5
|
||||
|
||||
static inline void hal_fem_ppi_setup(void)
|
||||
{
|
||||
nrf_ppi_channel_and_fork_endpoint_setup(
|
||||
@ -323,7 +269,6 @@ static inline void hal_fem_ppi_setup(void)
|
||||
*
|
||||
* Note: this PPI is not needed if we use a single TIMER instance in radio.c
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI 8
|
||||
|
||||
static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
{
|
||||
@ -343,7 +288,6 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
* Note: in nRF52X this PPI channel is forked for both capturing and clearing
|
||||
* timer on RADIO EVENTS_END.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI HAL_RADIO_END_TIME_CAPTURE_PPI
|
||||
|
||||
static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
{
|
||||
@ -372,19 +316,14 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
* 2 adjacent PPIs (9 & 10) and 2 adjacent PPI groups are used for this wiring;
|
||||
* <index> must be 0 or 1. <offset> must be a valid TIMER CC register offset.
|
||||
*/
|
||||
#if defined(CONFIG_SOC_NRF52805)
|
||||
/* Because nRF52805 has limited number of programmable PPI channels,
|
||||
* tIFS Trx SW switching on this SoC can be used only when pre-programmed
|
||||
* PPI channels are also in use, i.e. when TIMER0 is the event timer.
|
||||
*/
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 2
|
||||
#else
|
||||
#if (EVENT_TIMER_ID != 0) && defined(CONFIG_SOC_NRF52805)
|
||||
#error "tIFS Trx SW switch can be used on this SoC only with TIMER0 as the event timer"
|
||||
#endif
|
||||
#else /* -> !defined(CONFIG_SOC_NRF52805) */
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 9
|
||||
#endif
|
||||
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(index) \
|
||||
(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE + (index))
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(chan) \
|
||||
@ -399,15 +338,6 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
/* Wire the RADIO EVENTS_END event to one of the PPI GROUP TASK ENABLE task.
|
||||
* 2 adjacent PPI groups are used for this wiring. 'index' must be 0 or 1.
|
||||
*/
|
||||
#if defined(CONFIG_SOC_NRF52805)
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI 9
|
||||
#else
|
||||
#error "tIFS Trx SW switch can be used on this SoC only with TIMER0 as the event timer"
|
||||
#endif
|
||||
#else /* -> !defined(CONFIG_SOC_NRF52805) */
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI 11
|
||||
#endif
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT \
|
||||
((uint32_t)&(NRF_RADIO->EVENTS_END))
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_TASK(index) \
|
||||
@ -419,15 +349,6 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
* 2 adjacent PPIs (12 & 13) are used for this wiring; <index> must be 0 or 1.
|
||||
* <offset> must be a valid TIMER CC register offset.
|
||||
*/
|
||||
#if defined(CONFIG_SOC_NRF52805)
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 4
|
||||
#else
|
||||
#error "tIFS Trx SW switch can be used on this SoC only with TIMER0 as the event timer"
|
||||
#endif
|
||||
#else /* -> !defined(CONFIG_SOC_NRF52805) */
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 12
|
||||
#endif
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI(index) \
|
||||
(HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE + (index))
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(chan) \
|
||||
@ -526,14 +447,12 @@ static inline void hal_radio_sw_switch_cleanup(void)
|
||||
/* Wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
|
||||
* to RADIO TASKS_TXEN/RXEN task.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE 17
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(index) \
|
||||
(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE + (index))
|
||||
|
||||
/* Cancel the SW switch timer running considering S8 timing:
|
||||
* wire the RADIO EVENTS_RATEBOOST event to SW_SWITCH_TIMER TASKS_CAPTURE task.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI 19
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT \
|
||||
NRF_PPI->CH[HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI].EEP
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT \
|
||||
@ -648,71 +567,3 @@ static inline void hal_radio_sw_switch_ppi_group_setup(void)
|
||||
|
||||
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
|
||||
#endif /* CONFIG_SOC_SERIES_NRF51X || CONFIG_SOC_COMPATIBLE_NRF52X */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define HAL_USED_PPI_CHANNELS \
|
||||
(BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) | \
|
||||
BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) | \
|
||||
BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) | \
|
||||
BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) | \
|
||||
BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) | \
|
||||
BIT(HAL_EVENT_TIMER_START_PPI) | \
|
||||
BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) | \
|
||||
BIT(HAL_TRIGGER_CRYPT_PPI) | \
|
||||
BIT(HAL_TRIGGER_AAR_PPI) | \
|
||||
HAL_USED_PPI_CHANNELS_2 | HAL_USED_PPI_CHANNELS_3 | \
|
||||
HAL_USED_PPI_CHANNELS_4 | HAL_USED_PPI_CHANNELS_5 | \
|
||||
HAL_USED_PPI_CHANNELS_6)
|
||||
|
||||
#if defined(HAL_TRIGGER_RATEOVERRIDE_PPI)
|
||||
#define HAL_USED_PPI_CHANNELS_2 \
|
||||
BIT(HAL_TRIGGER_RATEOVERRIDE_PPI)
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_2 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_ENABLE_PALNA_PPI)
|
||||
#define HAL_USED_PPI_CHANNELS_3 \
|
||||
(BIT(HAL_ENABLE_PALNA_PPI) | \
|
||||
BIT(HAL_DISABLE_PALNA_PPI))
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_3 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_SW_SWITCH_TIMER_CLEAR_PPI)
|
||||
#define HAL_USED_PPI_CHANNELS_4 \
|
||||
(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE + 1) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE + 1))
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_4 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE)
|
||||
#define HAL_USED_PPI_CHANNELS_5 \
|
||||
(BIT(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE + 1) | \
|
||||
BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI))
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_5 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_ENABLE_FEM_PPI)
|
||||
#define HAL_USED_PPI_CHANNELS_6 \
|
||||
(BIT(HAL_ENABLE_FEM_PPI) | \
|
||||
BIT(HAL_DISABLE_FEM_PPI))
|
||||
#else
|
||||
#define HAL_USED_PPI_CHANNELS_6 0
|
||||
#endif
|
||||
|
||||
#if defined(SW_SWITCH_TIMER_TASK_GROUP_BASE)
|
||||
#define HAL_USED_PPI_GROUPS \
|
||||
(BIT(SW_SWITCH_TIMER_TASK_GROUP_BASE) | \
|
||||
BIT(SW_SWITCH_TIMER_TASK_GROUP_BASE + 1))
|
||||
#else
|
||||
#define HAL_USED_PPI_GROUPS 0
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <sys/util.h>
|
||||
#include "radio_nrf5_fem.h"
|
||||
|
||||
#if defined(CONFIG_BT_CTLR_TIFS_HW) || !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
|
||||
|
||||
/* PPI channel 20 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[0]
|
||||
* TEP: RADIO->TASKS_TXEN
|
||||
*/
|
||||
#define HAL_RADIO_ENABLE_TX_ON_TICK_PPI 20
|
||||
/* PPI channel 21 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[0]
|
||||
* TEP: RADIO->TASKS_RXEN
|
||||
*/
|
||||
#define HAL_RADIO_ENABLE_RX_ON_TICK_PPI 21
|
||||
|
||||
/* PPI channel 26 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_ADDRESS
|
||||
* TEP: TIMER0->TASKS_CAPTURE[1]
|
||||
*/
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 26
|
||||
|
||||
/* PPI channel 22 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[1]
|
||||
* TEP: RADIO->TASKS_DISABLE
|
||||
*/
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI 22
|
||||
|
||||
/* PPI channel 27 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_END
|
||||
* TEP: TIMER0->TASKS_CAPTURE[2]
|
||||
*/
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI 27
|
||||
|
||||
#else /* CONFIG_BT_CTLR_TIFS_HW || !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
|
||||
#define HAL_RADIO_ENABLE_ON_TICK_PPI 2
|
||||
#define HAL_RADIO_ENABLE_TX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
|
||||
#define HAL_RADIO_ENABLE_RX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 3
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI 4
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI 5
|
||||
|
||||
#endif /* CONFIG_BT_CTLR_TIFS_HW || !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
|
||||
/* Start event timer on RTC tick wire the RTC0 EVENTS_COMPARE[2] event to
|
||||
* EVENT_TIMER TASKS_START task.
|
||||
*/
|
||||
#define HAL_EVENT_TIMER_START_PPI 6
|
||||
|
||||
/* Capture event timer on Radio ready, wire the RADIO EVENTS_READY event to the
|
||||
* EVENT_TIMER TASKS_CAPTURE[<radio ready timer>] task.
|
||||
*/
|
||||
#define HAL_RADIO_READY_TIME_CAPTURE_PPI 7
|
||||
|
||||
/* Trigger encryption task upon address reception:
|
||||
* wire the RADIO EVENTS_ADDRESS event to the CCM TASKS_CRYPT task.
|
||||
*
|
||||
* PPI channel 25 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_ADDRESS
|
||||
* TEP: CCM->TASKS_CRYPT
|
||||
*/
|
||||
#define HAL_TRIGGER_CRYPT_PPI 25
|
||||
|
||||
/* Trigger automatic address resolution on Bit counter match:
|
||||
* wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task.
|
||||
*
|
||||
* PPI channel 23 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_BCMATCH
|
||||
* TEP: AAR->TASKS_START
|
||||
*/
|
||||
#define HAL_TRIGGER_AAR_PPI 23
|
||||
|
||||
/* Trigger Radio Rate override upon Rateboost event. */
|
||||
#if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI 14
|
||||
#endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
|
||||
|
||||
#define HAL_ENABLE_PALNA_PPI 15
|
||||
#define HAL_DISABLE_PALNA_PPI 16
|
||||
|
||||
#if defined(HAL_RADIO_FEM_IS_NRF21540)
|
||||
#define HAL_ENABLE_FEM_PPI 4
|
||||
#define HAL_DISABLE_FEM_PPI 5
|
||||
#endif /* HAL_RADIO_FEM_IS_NRF21540 */
|
||||
|
||||
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
|
||||
/* PPI setup used for SW-based auto-switching during TIFS. */
|
||||
|
||||
#if !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
|
||||
|
||||
/* Clear SW-switch timer on packet end:
|
||||
* wire the RADIO EVENTS_END event to SW_SWITCH_TIMER TASKS_CLEAR task.
|
||||
*
|
||||
* Note: this PPI is not needed if we use a single TIMER instance in radio.c
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI 8
|
||||
|
||||
#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
|
||||
/* Clear event timer (sw-switch timer) on Radio end:
|
||||
* wire the RADIO EVENTS_END event to the
|
||||
* EVENT_TIMER TASKS_CLEAR task.
|
||||
*
|
||||
* Note: in nRF52X this PPI channel is forked for both capturing and clearing
|
||||
* timer on RADIO EVENTS_END.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI HAL_RADIO_END_TIME_CAPTURE_PPI
|
||||
|
||||
#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
|
||||
/* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
|
||||
* to a PPI GROUP TASK DISABLE task (PPI group with index <index>).
|
||||
* 2 adjacent PPIs (9 & 10) and 2 adjacent PPI groups are used for this wiring;
|
||||
* <index> must be 0 or 1. <offset> must be a valid TIMER CC register offset.
|
||||
*/
|
||||
#if defined(CONFIG_SOC_NRF52805)
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 2
|
||||
#else /* CONFIG_SOC_NRF52805 */
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 9
|
||||
#endif
|
||||
|
||||
/* Wire the RADIO EVENTS_END event to one of the PPI GROUP TASK ENABLE task.
|
||||
* 2 adjacent PPI groups are used for this wiring. 'index' must be 0 or 1.
|
||||
*/
|
||||
#if defined(CONFIG_SOC_NRF52805)
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI 9
|
||||
#else /* CONFIG_SOC_NRF52805 */
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI 11
|
||||
#endif
|
||||
|
||||
/*Enable Radio at specific time-stamp:
|
||||
* wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
|
||||
* to RADIO TASKS_TXEN/RXEN task.
|
||||
* 2 adjacent PPIs (12 & 13) are used for this wiring; <index> must be 0 or 1.
|
||||
* <offset> must be a valid TIMER CC register offset.
|
||||
*/
|
||||
#if defined(CONFIG_SOC_NRF52805)
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 4
|
||||
#else /* CONFIG_SOC_NRF52805 */
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 12
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BT_CTLR_PHY_CODED) && \
|
||||
defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
|
||||
|
||||
/* Wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
|
||||
* to RADIO TASKS_TXEN/RXEN task.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE 17
|
||||
|
||||
/* Cancel the SW switch timer running considering S8 timing:
|
||||
* wire the RADIO EVENTS_RATEBOOST event to SW_SWITCH_TIMER TASKS_CAPTURE task.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI 19
|
||||
|
||||
#endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
|
||||
|
||||
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
|
||||
@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "radio_nrf5_fem.h"
|
||||
|
||||
#ifdef DPPI_PRESENT
|
||||
#include "radio_nrf5_dppi_resources.h"
|
||||
#else
|
||||
#include "radio_nrf5_ppi_resources.h"
|
||||
#endif
|
||||
|
||||
#if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || \
|
||||
defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
|
||||
#define HAL_PALNA_GPIOTE_CHAN 0
|
||||
#define HAL_PALNA_GPIOTE_MASK BIT(HAL_PALNA_GPIOTE_CHAN)
|
||||
#else
|
||||
#define HAL_PALNA_GPIOTE_MASK 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_RADIO_FEM_IS_NRF21540)
|
||||
#define HAL_PDN_GPIOTE_CHAN 1
|
||||
#define HAL_CSN_GPIOTE_CHAN 2
|
||||
#define HAL_PDN_CSN_GPIOTE_MASK (BIT(HAL_PDN_GPIOTE_CHAN) | BIT(HAL_CSN_GPIOTE_CHAN))
|
||||
#else
|
||||
#define HAL_PDN_CSN_GPIOTE_MASK 0
|
||||
#endif
|
||||
|
||||
/* Mask with all GPIOTE channels used by the bluetooth controller. */
|
||||
#define BT_CTLR_USED_GPIOTE_CHANNELS (HAL_PALNA_GPIOTE_MASK | HAL_PDN_CSN_GPIOTE_MASK)
|
||||
|
||||
/* Mask with all (D)PPI channels used by the bluetooth controller. */
|
||||
#define BT_CTLR_USED_PPI_CHANNELS \
|
||||
(BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) | \
|
||||
BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) | \
|
||||
BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) | \
|
||||
BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) | \
|
||||
BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) | \
|
||||
BIT(HAL_EVENT_TIMER_START_PPI) | \
|
||||
BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) | \
|
||||
BIT(HAL_TRIGGER_CRYPT_PPI) | \
|
||||
BIT(HAL_TRIGGER_AAR_PPI) | \
|
||||
BT_CTLR_USED_PPI_CHANNELS_2 | BT_CTLR_USED_PPI_CHANNELS_3 | \
|
||||
BT_CTLR_USED_PPI_CHANNELS_4 | BT_CTLR_USED_PPI_CHANNELS_5 | \
|
||||
BT_CTLR_USED_PPI_CHANNELS_6)
|
||||
|
||||
#if defined(HAL_TRIGGER_RATEOVERRIDE_PPI)
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_2 \
|
||||
BIT(HAL_TRIGGER_RATEOVERRIDE_PPI)
|
||||
#else
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_2 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_ENABLE_PALNA_PPI)
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_3 \
|
||||
(BIT(HAL_ENABLE_PALNA_PPI) | \
|
||||
BIT(HAL_DISABLE_PALNA_PPI))
|
||||
#else
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_3 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_SW_SWITCH_TIMER_CLEAR_PPI)
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_4 \
|
||||
(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE + 1) | \
|
||||
BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE + 1))
|
||||
#else
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_4 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE)
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_5 \
|
||||
(BIT(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE) | \
|
||||
BIT(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE + 1) | \
|
||||
BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI))
|
||||
#else
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_5 0
|
||||
#endif
|
||||
|
||||
#if defined(HAL_ENABLE_FEM_PPI)
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_6 \
|
||||
(BIT(HAL_ENABLE_FEM_PPI) | \
|
||||
BIT(HAL_DISABLE_FEM_PPI))
|
||||
#else
|
||||
#define BT_CTLR_USED_PPI_CHANNELS_6 0
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
|
||||
#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
|
||||
#endif
|
||||
|
||||
/* Mask with all (D)PPI groups used by the bluetooth controller. */
|
||||
#if defined(SW_SWITCH_TIMER_TASK_GROUP_BASE)
|
||||
#define BT_CTLR_USED_PPI_GROUPS \
|
||||
(BIT(SW_SWITCH_TIMER_TASK_GROUP_BASE) | \
|
||||
BIT(SW_SWITCH_TIMER_TASK_GROUP_BASE + 1))
|
||||
#else
|
||||
#define BT_CTLR_USED_PPI_GROUPS 0
|
||||
#endif
|
||||
@ -193,8 +193,6 @@
|
||||
#define SW_SWITCH_TIMER NRF_TIMER1
|
||||
#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0
|
||||
#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
|
||||
#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
|
||||
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
|
||||
|
||||
static inline void hal_radio_reset(void)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user