diff --git a/boards/arm64/nxp_ls1046ardb/CMakeLists.txt b/boards/arm64/nxp_ls1046ardb/CMakeLists.txt new file mode 100644 index 00000000000..9881313609a --- /dev/null +++ b/boards/arm64/nxp_ls1046ardb/CMakeLists.txt @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm64/nxp_ls1046ardb/Kconfig.board b/boards/arm64/nxp_ls1046ardb/Kconfig.board new file mode 100644 index 00000000000..5986971533e --- /dev/null +++ b/boards/arm64/nxp_ls1046ardb/Kconfig.board @@ -0,0 +1,8 @@ +# +# Copyright 2021 NXP +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_NXP_LS1046ARDB + bool "NXP Layerscape ls1046ardb" + depends on SOC_SERIES_LS1046A diff --git a/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig b/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig new file mode 100644 index 00000000000..1896c014d5c --- /dev/null +++ b/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig @@ -0,0 +1,8 @@ +# +# Copyright 2021 NXP +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD + default "nxp_ls1046ardb" + depends on BOARD_NXP_LS1046ARDB diff --git a/boards/arm64/nxp_ls1046ardb/board.cmake b/boards/arm64/nxp_ls1046ardb/board.cmake new file mode 100644 index 00000000000..9881313609a --- /dev/null +++ b/boards/arm64/nxp_ls1046ardb/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm64/nxp_ls1046ardb/doc/index.rst b/boards/arm64/nxp_ls1046ardb/doc/index.rst new file mode 100644 index 00000000000..bed0c29abdc --- /dev/null +++ b/boards/arm64/nxp_ls1046ardb/doc/index.rst @@ -0,0 +1,124 @@ +.. _nxp_ls1046ardb: + +NXP LS1046A RDB +################################# + +Overview +******** + +The LS1046A reference design board (RDB) is a high-performance computing, +evaluation, and development platform that supports the Layerscape LS1046A +architecture processor. The LS1046ARDB board supports the Layerscape LS1046A +processor and is optimized to support the DDR4 memory and a full complement +of high-speed SerDes ports. + +The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72 +cores with packet processing acceleration and high-speed peripherals. The +impressive performance of more than 32,000 CoreMarks, paired with 10 Gb +Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an +excellent combination for a range of enterprise and service provider +networking, storage, security and industrial applications. + +Hardware +******** + +LS1046A RDB boards supports the following features: + + +- Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed +- Supports 8 GB DDR4 SDRAM memory +- SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi + memory device +- One 512 MB SLC NAND flash with ECC support (1.8 V) +- CPLD connection: 8-bit registers in CPLD to configure mux/demux selections +- Support two 64 MB onboard QSPI NOR flash memories +- USB: + - Two USB 3.0 controllers with integrated PHYs. + - One USB1 3.0 port is connected to a Type A host connector. + - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector. + - One USB2.0 is connected to miniPCIe connector . +- Ethernet: + - Supports SGMII 1G PHYs at Lane 2 and Lane 3 + - Supports SFP+module with XFI retimers + - Supports AQR106/107 10G PHY with XFI/2.5G SGMII +- PCIe and SATA: + - Mini PCIe express x1 (Gen1/2/3)card + - Standard PCIe x1 (Gen1/2/3) card + - Standard PCIe x1 (Gen1/2/3) card + - One SATA 3.0 connector + +Supported Features +================== + +NXP LS1046A RDB board default configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-400 | on-chip | GICv2 interrupt controller | ++-----------+------------+--------------------------------------+ +| ARM TIMER | on-chip | System Clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | NS16550 compatible serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features are not supported by the Zephyr kernel. + +The default configuration can be found in the defconfig file: + + ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig`` + +There are two serial port on the board: uart1 and uart2, Zephyr is using +uart2 as serial console. + +Programming and Debugging +************************* + +Use the following configuration to run basic Zephyr applications and +kernel tests on LS1046A RDB board. For example, with the :ref:`synchronization_sample`: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: nxp_ls1046ardb + :goals: run + +This will build an image with the synchronization sample app. + +Use u-boot to load and kick Zephyr.bin: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off;go 0xc0000000; + +It will isplay the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 0 on nxp_ls1046ardb! + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 0 on nxp_ls1046ardb! + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 0 on nxp_ls1046ardb! + +Flashing +======== + +Zephyr image can be loaded in DDR memory at address 0xc0000000 from SD Card, +EMMC, QSPI Flash or downloaded from network in uboot. + +Debugging +========= + +LS1046A RDB board includes one JTAG connector on board, connect it to +CodeWarrior TAP for debugging. + +References +========== + +`Layerscape LS1046A Reference Design Board `_ + +`LS1046A Reference Manual `_ diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.dts b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.dts new file mode 100644 index 00000000000..a36842d6ffe --- /dev/null +++ b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.dts @@ -0,0 +1,78 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include + +/ { + model = "NXP ls1046a RDB"; + compatible = "fsl,ls1046ardb"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + label = "arch_timer"; + }; + + gic: interrupt-controller@1410000 { + compatible = "arm,gic"; + reg = <0x01410000 0x10000>, /* GICD */ + <0x0142f000 0x1000>; /* GICC */ + interrupt-controller; + #interrupt-cells = <4>; + label = "GIC"; + status = "okay"; + }; + + uart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550"; + reg = <0x21c0600 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <350000000>; + label = "UART_1"; + }; + + sram0: memory@c0000000 { + reg = <0xc0000000 DT_SIZE_M(1)>; + }; + +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml new file mode 100644 index 00000000000..6a04dbcc367 --- /dev/null +++ b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml @@ -0,0 +1,8 @@ +identifier: nxp_ls1046ardb +name: NXP LS1046ARDB +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig new file mode 100644 index 00000000000..3e85b4e443e --- /dev/null +++ b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_SOC_SERIES_LS1046A=y +CONFIG_SOC_LS1046A=y +CONFIG_BOARD_NXP_LS1046ARDB=y +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +# 1.8GHz system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1800000000 + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_AARCH64_IMAGE_HEADER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_NS16550=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y