clock control:stm32: provide STM32Cube LL based driver
This new clock control driver aims at providing a lightweight generic driver to the whole stm32 family. Driver is based on LL Cube API and hence is for now available only for STM32 supporting this API: stm32f3xx and stm32l4xx. Other families should be supported soon. Once globally supported, this unique driver will also help reducing the impact of stm32 clock control heterogeneity in other drivers. Change-Id: Id15a8d0d44f03809b2907ef10d6877700459e674 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Maureen Helm
parent
b4b395845a
commit
58c8d15147
@ -44,6 +44,8 @@ source "drivers/clock_control/Kconfig.nrf5"
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source "drivers/clock_control/Kconfig.quark_se"
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source "drivers/clock_control/Kconfig.stm32"
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source "drivers/clock_control/Kconfig.stm32f10x"
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source "drivers/clock_control/Kconfig.stm32f107xx"
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186
drivers/clock_control/Kconfig.stm32
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186
drivers/clock_control/Kconfig.stm32
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@ -0,0 +1,186 @@
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# Kconfig - STM32 MCU clock control driver config
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#
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# Copyright (c) 2017 Linaro
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_FAMILY_STM32
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menuconfig CLOCK_CONTROL_STM32_CUBE
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bool
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prompt "STM32 Reset & Clock Control"
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depends on CLOCK_CONTROL
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default n if SOC_SERIES_STM32
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help
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Enable driver for Reset & Clock Control subsystem found
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in STM32 family of MCUs
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config CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY
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int "Clock Control Device Priority"
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default 1
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depends on CLOCK_CONTROL_STM32_CUBE
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help
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This option controls the priority of clock control
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device initialization. Higher priority ensures that the device
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is initialized earlier in the startup cycle. If unsure, leave
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at default value 1
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choice
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prompt "STM32 System Clock Source"
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depends on CLOCK_CONTROL_STM32_CUBE
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default CLOCK_STM32_SYSCLK_SRC_PLL
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config CLOCK_STM32_SYSCLK_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of SYSCLK
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config CLOCK_STM32_SYSCLK_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of SYSCLK
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config CLOCK_STM32_SYSCLK_SRC_PLL
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bool "PLL"
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help
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Use PLL as source of SYSCLK
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endchoice
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config CLOCK_STM32_HSE_BYPASS
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bool "HSE bypass"
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depends on CLOCK_CONTROL_STM32_CUBE && (CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE)
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help
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Enable this option to bypass external high-speed clock (HSE).
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config CLOCK_STM32_HSE_CLOCK
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int "HSE clock value"
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depends on CLOCK_CONTROL_STM32_CUBE && (CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE)
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help
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Value of external high-speed clock (HSE).
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choice
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prompt "STM32 PLL Clock Source"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default CLOCK_STM32_PLL_SRC_HSI
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config CLOCK_STM32_PLL_SRC_MSI
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bool "MSI"
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help
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Use MSI as source of PLL
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config CLOCK_STM32_PLL_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of PLL
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config CLOCK_STM32_PLL_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of PLL
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endchoice
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if SOC_SERIES_STM32F3X
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config CLOCK_STM32_PLL_PREDIV
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int "PREDIV Prescaler"
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depends on CLOCK_CONTROL_STM32_CUBE
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default 1
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range 1 16
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help
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PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16.
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config CLOCK_STM32_PLL_PREDIV1
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int "PREDIV1 Prescaler"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_PLL_SRC_HSE && (SOC_STM32F302XE || SOC_STM32F303XE || SOC_STM32F398XX)
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default 1
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range 1 16
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help
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PREDIV is PLLSCR clock signal prescaler, present on STM32F302xE, STM32F303xE and STM32F39xx SoCs.
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Allowed values: 1 - 16.
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config CLOCK_STM32_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 9
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range 2 16
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help
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PLL multiplier, allowed values: 2-16. PLL output must not exceed 72MHz.
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endif # SOC_SERIES_STM32F3X
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if SOC_SERIES_STM32L4X
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config CLOCK_STM32_PLL_M_DIVISOR
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int "PLL divisor"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 8
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help
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PLL divisor, allowed values: 1-8. With this ensure that the PLL
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VCO input frequency ranges from 4 to 16MHz.
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 20
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range 8 86
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help
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PLL multiplier, allowed values: 2-16. PLL output must not
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exceed 344MHz.
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL P Divisor"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 7
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range 0 17
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help
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PLL P Output divisor, allowed values: 0, 7, 17.
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "PLL Q Divisor"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 0 8
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help
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PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.
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config CLOCK_STM32_PLL_R_DIVISOR
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int "PLL R Divisor"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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range 0 8
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help
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PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.
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endif # SOC_SERIES_STM32L4X
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config CLOCK_STM32_AHB_PRESCALER
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int "AHB prescaler"
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depends on CLOCK_CONTROL_STM32_CUBE
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default 0
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range 0 512
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help
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AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32_APB1_PRESCALER
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int "APB1 prescaler"
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depends on CLOCK_CONTROL_STM32_CUBE
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default 1
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range 1 16
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help
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APB1 Low speed clock (PCLK1) prescaler, allowed values:
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1, 2, 4, 8, 16
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config CLOCK_STM32_APB2_PRESCALER
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int "APB2 prescaler"
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depends on CLOCK_CONTROL_STM32_CUBE
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default 1
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range 1 16
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help
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APB2 High speed clock (PCLK2) prescaler, allowed values:
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1, 2, 4, 8, 16
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endif # SOC_FAMILY_STM32
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@ -1,8 +1,14 @@
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obj-$(CONFIG_CLOCK_CONTROL_NRF5) += nrf5_power_clock.o
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obj-$(CONFIG_CLOCK_CONTROL_QUARK_SE) += quark_se_clock_control.o
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ifeq ($(CONFIG_CLOCK_CONTROL_STM32_CUBE),y)
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obj-y += stm32_ll_clock.o
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obj-$(CONFIG_SOC_SERIES_STM32L4X) += stm32l4x_ll_clock.o
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obj-$(CONFIG_SOC_SERIES_STM32F3X) += stm32f3x_ll_clock.o
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else
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obj-$(CONFIG_CLOCK_CONTROL_STM32F10X) += stm32f10x_clock.o
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obj-$(CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE) += stm32f107xx_clock.o
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obj-$(CONFIG_CLOCK_CONTROL_STM32F3X) += stm32f3x_clock.o
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obj-$(CONFIG_CLOCK_CONTROL_STM32F4X) += stm32f4x_clock.o
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obj-$(CONFIG_CLOCK_CONTROL_STM32L4X) += stm32l4x_clock.o
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endif
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obj-$(CONFIG_CLOCK_CONTROL_BEETLE) += beetle_clock_control.o
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351
drivers/clock_control/stm32_ll_clock.c
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351
drivers/clock_control/stm32_ll_clock.c
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@ -0,0 +1,351 @@
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/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <soc_registers.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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#include "stm32_ll_clock.h"
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/**
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* @brief helper for mapping a setting to register value
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*/
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uint32_t map_reg_val(const struct regval_map *map, size_t cnt, int val)
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{
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for (int i = 0; i < cnt; i++) {
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if (map[i].val == val) {
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return map[i].reg;
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}
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}
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return 0;
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}
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/**
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* @brief map AHB prescaler setting to register value
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*/
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static uint32_t ahb_prescaler(int prescaler)
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{
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const struct regval_map ahb_map[] = {
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{1, LL_RCC_SYSCLK_DIV_1},
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{2, LL_RCC_SYSCLK_DIV_2},
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{4, LL_RCC_SYSCLK_DIV_4},
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{8, LL_RCC_SYSCLK_DIV_8},
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{16, LL_RCC_SYSCLK_DIV_16},
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{64, LL_RCC_SYSCLK_DIV_64},
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{128, LL_RCC_SYSCLK_DIV_128},
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{256, LL_RCC_SYSCLK_DIV_256},
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{512, LL_RCC_SYSCLK_DIV_512},
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};
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return map_reg_val(ahb_map, ARRAY_SIZE(ahb_map), prescaler);
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}
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/**
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* @brief map APB1 prescaler setting to register value
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*/
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static uint32_t apb1_prescaler(int prescaler)
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{
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const struct regval_map apb1_map[] = {
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{1, LL_RCC_APB1_DIV_1},
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{2, LL_RCC_APB1_DIV_2},
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{4, LL_RCC_APB1_DIV_4},
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{8, LL_RCC_APB1_DIV_8},
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{16, LL_RCC_APB1_DIV_16},
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};
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return map_reg_val(apb1_map, ARRAY_SIZE(apb1_map), prescaler);
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}
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/**
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* @brief map APB2 prescaler setting to register value
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*/
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static uint32_t apb2_prescaler(int prescaler)
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{
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const struct regval_map apb2_map[] = {
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{1, LL_RCC_APB2_DIV_1},
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{2, LL_RCC_APB2_DIV_2},
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{4, LL_RCC_APB2_DIV_4},
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{8, LL_RCC_APB2_DIV_8},
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{16, LL_RCC_APB2_DIV_16},
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};
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return map_reg_val(apb2_map, ARRAY_SIZE(apb2_map), prescaler);
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}
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/**
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* @brief fill in AHB/APB buses configuration structure
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*/
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static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
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{
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clk_init->AHBCLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_AHB_PRESCALER);
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clk_init->APB1CLKDivider = apb1_prescaler(
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CONFIG_CLOCK_STM32_APB1_PRESCALER);
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clk_init->APB2CLKDivider = apb2_prescaler(
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CONFIG_CLOCK_STM32_APB2_PRESCALER);
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}
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static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
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{
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return clock / prescaler;
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}
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static inline int stm32_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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LL_AHB1_GRP1_EnableClock(pclken->enr);
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break;
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#ifdef CONFIG_SOC_SERIES_STM32L4X
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_EnableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X */
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_EnableClock(pclken->enr);
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break;
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#ifdef CONFIG_SOC_SERIES_STM32L4X
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_EnableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X */
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_EnableClock(pclken->enr);
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break;
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}
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return 0;
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}
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static inline int stm32_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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LL_AHB1_GRP1_DisableClock(pclken->enr);
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break;
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#ifdef CONFIG_SOC_SERIES_STM32L4X
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_DisableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X */
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_DisableClock(pclken->enr);
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break;
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#ifdef CONFIG_SOC_SERIES_STM32L4X
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_DisableClock(pclken->enr);
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break;
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#endif
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_DisableClock(pclken->enr);
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break;
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}
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(struct device *clock,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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/*
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* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
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* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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* since it will be updated after clock configuration and hence
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* more likely to contain actual clock speed
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*/
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uint32_t ahb_clock = SystemCoreClock;
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uint32_t apb1_clock = get_bus_clock(ahb_clock,
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CONFIG_CLOCK_STM32_APB1_PRESCALER);
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uint32_t apb2_clock = get_bus_clock(ahb_clock,
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CONFIG_CLOCK_STM32_APB2_PRESCALER);
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ARG_UNUSED(clock);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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case STM32_CLOCK_BUS_AHB2:
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*rate = ahb_clock;
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break;
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case STM32_CLOCK_BUS_APB1:
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#ifdef CONFIG_SOC_SERIES_STM32L4X
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case STM32_CLOCK_BUS_APB1_2:
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#endif
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*rate = apb1_clock;
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break;
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case STM32_CLOCK_BUS_APB2:
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*rate = apb2_clock;
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break;
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}
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return 0;
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}
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static struct clock_control_driver_api stm32_clock_control_api = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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};
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static int stm32_clock_control_init(struct device *dev)
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{
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LL_UTILS_ClkInitTypeDef s_ClkInitStruct;
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ARG_UNUSED(dev);
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/* configure clock for AHB/APB buses */
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config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct);
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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LL_UTILS_PLLInitTypeDef s_PLLInitStruct;
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/* configure PLL input settings */
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config_pll_init(&s_PLLInitStruct);
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/* Disable PLL before configuration */
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LL_RCC_PLL_Disable();
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#ifdef CONFIG_CLOCK_STM32_PLL_SRC_MSI
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/* Switch to PLL with MSI as clock source */
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LL_PLL_ConfigSystemClock_MSI(&s_PLLInitStruct, &s_ClkInitStruct);
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/* Disable other clocks */
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LL_RCC_HSI_Disable();
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LL_RCC_HSE_Disable();
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#elif CONFIG_CLOCK_STM32_PLL_SRC_HSI
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/* Switch to PLL with HSI as clock source */
|
||||
LL_PLL_ConfigSystemClock_HSI(&s_PLLInitStruct, &s_ClkInitStruct);
|
||||
|
||||
/* Disable other clocks */
|
||||
LL_RCC_HSE_Disable();
|
||||
LL_RCC_MSI_Disable();
|
||||
|
||||
#elif CONFIG_CLOCK_STM32_PLL_SRC_HSE
|
||||
int hse_bypass = LL_UTILS_HSEBYPASS_OFF;
|
||||
|
||||
#ifdef CONFIG_CLOCK_STM32_HSE_BYPASS
|
||||
hse_bypass = LL_UTILS_HSEBYPASS_ON;
|
||||
#endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */
|
||||
|
||||
/* Switch to PLL with HSE as clock source */
|
||||
LL_PLL_ConfigSystemClock_HSE(CONFIG_CLOCK_STM32_HSE_CLOCK, hse_bypass,
|
||||
&s_PLLInitStruct,
|
||||
&s_ClkInitStruct);
|
||||
|
||||
/* Disable other clocks */
|
||||
LL_RCC_HSI_Disable();
|
||||
LL_RCC_MSI_Disable();
|
||||
|
||||
#endif /* CONFIG_CLOCK_STM32_PLL_SRC_... */
|
||||
|
||||
#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE
|
||||
|
||||
/* Enable HSE if not enabled */
|
||||
if (LL_RCC_HSE_IsReady() != 1) {
|
||||
/* Check if need to enable HSE bypass feature or not */
|
||||
#ifdef CONFIG_CLOCK_STM32_HSE_BYPASS
|
||||
LL_RCC_HSE_EnableBypass();
|
||||
#else
|
||||
LL_RCC_HSE_DisableBypass();
|
||||
#endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */
|
||||
|
||||
/* Enable HSE */
|
||||
LL_RCC_HSE_Enable();
|
||||
while (LL_RCC_HSE_IsReady() != 1) {
|
||||
/* Wait for HSE ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Set HSE as SYSCLCK source */
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
|
||||
LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
|
||||
}
|
||||
|
||||
/* Update SystemCoreClock variable */
|
||||
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(
|
||||
CONFIG_CLOCK_STM32_HSE_CLOCK,
|
||||
s_ClkInitStruct.AHBCLKDivider));
|
||||
|
||||
/* Set APB1 & APB2 prescaler*/
|
||||
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
|
||||
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
|
||||
|
||||
/* Set flash latency */
|
||||
/* HSI used as SYSCLK, set latency to 0 */
|
||||
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
|
||||
|
||||
/* Disable other clocks */
|
||||
LL_RCC_HSI_Disable();
|
||||
LL_RCC_MSI_Disable();
|
||||
LL_RCC_PLL_Disable();
|
||||
|
||||
#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
|
||||
|
||||
/* Enable HSI if not enabled */
|
||||
if (LL_RCC_HSI_IsReady() != 1) {
|
||||
/* Enable HSI */
|
||||
LL_RCC_HSI_Enable();
|
||||
while (LL_RCC_HSI_IsReady() != 1) {
|
||||
/* Wait for HSI ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Set HSI as SYSCLCK source */
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
|
||||
LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
|
||||
}
|
||||
|
||||
/* Update SystemCoreClock variable */
|
||||
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(HSI_VALUE,
|
||||
s_ClkInitStruct.AHBCLKDivider));
|
||||
|
||||
/* Set APB1 & APB2 prescaler*/
|
||||
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
|
||||
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
|
||||
|
||||
/* Set flash latency */
|
||||
/* HSI used as SYSCLK, set latency to 0 */
|
||||
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
|
||||
|
||||
/* Disable other clocks */
|
||||
LL_RCC_HSE_Disable();
|
||||
LL_RCC_MSI_Disable();
|
||||
LL_RCC_PLL_Disable();
|
||||
|
||||
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_... */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCC device, note that priority is intentionally set to 1 so
|
||||
* that the device init runs just after SOC init
|
||||
*/
|
||||
DEVICE_AND_API_INIT(rcc_stm32, STM32_CLOCK_CONTROL_NAME,
|
||||
&stm32_clock_control_init,
|
||||
NULL, NULL,
|
||||
PRE_KERNEL_1,
|
||||
CONFIG_CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY,
|
||||
&stm32_clock_control_api);
|
||||
23
drivers/clock_control/stm32_ll_clock.h
Normal file
23
drivers/clock_control/stm32_ll_clock.h
Normal file
@ -0,0 +1,23 @@
|
||||
/*
|
||||
*
|
||||
* Copyright (c) 2017 Linaro Limited.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _STM32_LL_CLOCK_H_
|
||||
#define _STM32_LL_CLOCK_H_
|
||||
|
||||
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit);
|
||||
|
||||
struct regval_map {
|
||||
int val;
|
||||
uint32_t reg;
|
||||
};
|
||||
|
||||
uint32_t map_reg_val(const struct regval_map *map, size_t cnt, int val);
|
||||
|
||||
/* */
|
||||
void LL_AHB2_GRP1_EnableClock(uint32_t Periphs);
|
||||
void LL_RCC_MSI_Disable(void);
|
||||
#endif /* _STM32_LL_CLOCK_H_ */
|
||||
73
drivers/clock_control/stm32f3x_ll_clock.c
Normal file
73
drivers/clock_control/stm32f3x_ll_clock.c
Normal file
@ -0,0 +1,73 @@
|
||||
/*
|
||||
*
|
||||
* Copyright (c) 2017 Linaro Limited.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#include <soc.h>
|
||||
#include <soc_registers.h>
|
||||
#include <clock_control.h>
|
||||
#include <misc/util.h>
|
||||
#include <clock_control/stm32_clock_control.h>
|
||||
#include "stm32_ll_clock.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
|
||||
|
||||
/**
|
||||
* @brief fill in pll configuration structure
|
||||
*/
|
||||
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
|
||||
{
|
||||
/*
|
||||
* PLL MUL
|
||||
* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
|
||||
* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
|
||||
* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
|
||||
* ...
|
||||
* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
|
||||
*/
|
||||
pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
|
||||
<< RCC_CFGR_PLLMUL_Pos);
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
/* PREDIV support is a specific RCC configuration present on */
|
||||
/* following SoCs: STM32F302XE, STM32F303xE and STM32F398xx */
|
||||
/* cf Reference manual for more details */
|
||||
#if defined(CONFIG_CLOCK_STM32_PLL_SRC_HSI)
|
||||
pllinit->PLLDiv = LL_RCC_PLLSOURCE_HSI_DIV_2;
|
||||
#else
|
||||
/*
|
||||
* PLL DIV
|
||||
* 1 -> LL_RCC_PLLSOURCE_HSE_DIV_1 -> 0x00010000
|
||||
* 2 -> LL_RCC_PLLSOURCE_HSE_DIV_2 -> 0x00010001
|
||||
* 3 -> LL_RCC_PLLSOURCE_HSE_DIV_3 -> 0x00010002
|
||||
* ...
|
||||
* 16 -> LL_RCC_PLLSOURCE_HSE_DIV_16 -> 0x0001000F
|
||||
*/
|
||||
pllinit->PLLDiv = (RCC_CFGR_PLLSRC_HSE_PREDIV |
|
||||
(CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1));
|
||||
#endif /* CONFIG_CLOCK_STM32_PLL_SRC_HSI */
|
||||
#else
|
||||
/*
|
||||
* PLL Prediv
|
||||
* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
|
||||
* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
|
||||
* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
|
||||
* ...
|
||||
* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
|
||||
*/
|
||||
pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV - 1;
|
||||
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
|
||||
|
||||
/**
|
||||
* @brief Function kept for driver genericity
|
||||
*/
|
||||
void LL_RCC_MSI_Disable(void)
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
62
drivers/clock_control/stm32l4x_ll_clock.c
Normal file
62
drivers/clock_control/stm32l4x_ll_clock.c
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
*
|
||||
* Copyright (c) 2017 Linaro Limited.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#include <soc.h>
|
||||
#include <soc_registers.h>
|
||||
#include <clock_control.h>
|
||||
#include <misc/util.h>
|
||||
#include <clock_control/stm32_clock_control.h>
|
||||
#include "stm32_ll_clock.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
|
||||
|
||||
/**
|
||||
* @brief map PLLM setting to register value
|
||||
*/
|
||||
static uint32_t pllm(int prescaler)
|
||||
{
|
||||
const struct regval_map map[] = {
|
||||
{1, LL_RCC_PLLM_DIV_1},
|
||||
{2, LL_RCC_PLLM_DIV_2},
|
||||
{3, LL_RCC_PLLM_DIV_3},
|
||||
{4, LL_RCC_PLLM_DIV_4},
|
||||
{5, LL_RCC_PLLM_DIV_5},
|
||||
{6, LL_RCC_PLLM_DIV_6},
|
||||
{7, LL_RCC_PLLM_DIV_7},
|
||||
{8, LL_RCC_PLLM_DIV_8},
|
||||
};
|
||||
|
||||
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief map PLLR setting to register value
|
||||
*/
|
||||
static uint32_t pllr(int prescaler)
|
||||
{
|
||||
const struct regval_map map[] = {
|
||||
{2, LL_RCC_PLLR_DIV_2},
|
||||
{4, LL_RCC_PLLR_DIV_4},
|
||||
{6, LL_RCC_PLLR_DIV_6},
|
||||
{8, LL_RCC_PLLR_DIV_8},
|
||||
};
|
||||
|
||||
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief fill in pll configuration structure
|
||||
*/
|
||||
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
|
||||
{
|
||||
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
|
||||
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
|
||||
pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
|
||||
}
|
||||
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
|
||||
@ -11,6 +11,7 @@ endif
|
||||
ifdef CONFIG_SOC_SERIES_STM32F3X
|
||||
obj-y += stm32f3xx/drivers/src/stm32f3xx_hal.o
|
||||
obj-y += stm32f3xx/drivers/src/stm32f3xx_hal_rcc.o
|
||||
obj-$(CONFIG_CLOCK_CONTROL_STM32_CUBE) += stm32f3xx/drivers/src/stm32f3xx_ll_utils.o
|
||||
obj-$(CONFIG_SERIAL_HAS_DRIVER) += stm32f3xx/drivers/src/stm32f3xx_hal_uart.o
|
||||
obj-y += stm32f3xx/soc/system_stm32f3xx.o
|
||||
endif
|
||||
@ -31,6 +32,7 @@ endif
|
||||
ifdef CONFIG_SOC_SERIES_STM32L4X
|
||||
obj-y += stm32l4xx/drivers/src/stm32l4xx_hal.o
|
||||
obj-y += stm32l4xx/drivers/src/stm32l4xx_hal_rcc.o
|
||||
obj-$(CONFIG_CLOCK_CONTROL_STM32_CUBE) += stm32l4xx/drivers/src/stm32l4xx_ll_utils.o
|
||||
obj-$(CONFIG_PWM) += stm32l4xx/drivers/src/stm32l4xx_hal_tim.o
|
||||
obj-$(CONFIG_SERIAL_HAS_DRIVER) += stm32l4xx/drivers/src/stm32l4xx_hal_uart.o
|
||||
obj-y += stm32l4xx/soc/system_stm32l4xx.o
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* Copyright (c) 2016 Open-RnD Sp. z o.o.
|
||||
* Copyright (c) 2016 BayLibre, SAS
|
||||
* Copyright (c) 2016 RnDity Sp. z o.o.
|
||||
* Copyright (c) 2017 Linaro Limited.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -23,4 +24,20 @@
|
||||
#include "stm32l4x_clock_control.h"
|
||||
#endif
|
||||
|
||||
/* Bus */
|
||||
enum {
|
||||
STM32_CLOCK_BUS_AHB1,
|
||||
STM32_CLOCK_BUS_AHB2,
|
||||
STM32_CLOCK_BUS_APB1,
|
||||
#ifdef CONFIG_SOC_SERIES_STM32L4X
|
||||
STM32_CLOCK_BUS_APB1_2,
|
||||
#endif
|
||||
STM32_CLOCK_BUS_APB2,
|
||||
};
|
||||
|
||||
struct stm32_pclken {
|
||||
uint32_t bus;
|
||||
uint32_t enr;
|
||||
};
|
||||
|
||||
#endif /* _STM32_CLOCK_CONTROL_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user