diff --git a/subsys/bluetooth/controller/CMakeLists.txt b/subsys/bluetooth/controller/CMakeLists.txt index f5a70c9dda6..72b4a07a85a 100644 --- a/subsys/bluetooth/controller/CMakeLists.txt +++ b/subsys/bluetooth/controller/CMakeLists.txt @@ -7,7 +7,7 @@ zephyr_library_sources( hal/nrf5/cntr.c hal/nrf5/rand.c hal/nrf5/ecb.c - hal/nrf5/radio.c + hal/nrf5/radio/radio.c ticker/ticker.c ll_sw/ctrl.c ll_sw/crypto.c diff --git a/subsys/bluetooth/controller/hal/nrf5/radio.c b/subsys/bluetooth/controller/hal/nrf5/radio/radio.c similarity index 58% rename from subsys/bluetooth/controller/hal/nrf5/radio.c rename to subsys/bluetooth/controller/hal/nrf5/radio/radio.c index df304ee8ecb..04e908c0c9e 100644 --- a/subsys/bluetooth/controller/hal/nrf5/radio.c +++ b/subsys/bluetooth/controller/hal/nrf5/radio/radio.c @@ -11,6 +11,7 @@ #include "hal/ccm.h" #include "hal/radio.h" #include "ll_sw/pdu.h" +#include "radio_nrf5.h" #if defined(CONFIG_SOC_SERIES_NRF51X) #define RADIO_PDU_LEN_MAX (BIT(5) - 1) @@ -20,6 +21,7 @@ #error "Platform not defined." #endif + static radio_isr_fp sfp_radio_isr; void isr_radio(void) @@ -65,44 +67,7 @@ void radio_setup(void) radio_gpio_lna_off(); #endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */ -#if defined(CONFIG_SOC_SERIES_NRF52X) - struct { - u32_t volatile reserved_0[0x5a0 >> 2]; - u32_t volatile bridge_type; - u32_t volatile reserved_1[((0xe00 - 0x5a0) >> 2) - 1]; - struct { - u32_t volatile CPU0; - u32_t volatile SPIS1; - u32_t volatile RADIO; - u32_t volatile ECB; - u32_t volatile CCM; - u32_t volatile AAR; - u32_t volatile SAADC; - u32_t volatile UARTE; - u32_t volatile SERIAL0; - u32_t volatile SERIAL2; - u32_t volatile NFCT; - u32_t volatile I2S; - u32_t volatile PDM; - u32_t volatile PWM; - } RAMPRI; - } volatile *NRF_AMLI = (void volatile *)0x40000000UL; - - NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.SPIS1 = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.RADIO = 0x00000000UL; - NRF_AMLI->RAMPRI.ECB = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.CCM = 0x00000000UL; - NRF_AMLI->RAMPRI.AAR = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.SAADC = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.UARTE = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.SERIAL0 = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.SERIAL2 = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.NFCT = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.I2S = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.PDM = 0xFFFFFFFFUL; - NRF_AMLI->RAMPRI.PWM = 0xFFFFFFFFUL; -#endif /* CONFIG_SOC_SERIES_NRF52X */ + hal_radio_ram_prio_setup(); } void radio_reset(void) @@ -121,49 +86,7 @@ void radio_phy_set(u8_t phy, u8_t flags) { u32_t mode; - switch (phy) { - case BIT(0): - default: - mode = RADIO_MODE_MODE_Ble_1Mbit; - -#if defined(CONFIG_SOC_NRF52840) - /* Workaround: nRF52840 Engineering A Errata ID 164 */ - *(volatile u32_t *)0x4000173c &= ~0x80000000; -#endif /* CONFIG_SOC_NRF52840 */ - break; - -#if defined(CONFIG_SOC_SERIES_NRF51X) - case BIT(1): - mode = RADIO_MODE_MODE_Nrf_2Mbit; - break; - -#elif defined(CONFIG_SOC_SERIES_NRF52X) - case BIT(1): - mode = RADIO_MODE_MODE_Ble_2Mbit; - -#if defined(CONFIG_SOC_NRF52840) - /* Workaround: nRF52840 Engineering A Errata ID 164 */ - *(volatile u32_t *)0x4000173c &= ~0x80000000; -#endif /* CONFIG_SOC_NRF52840 */ - break; - -#if defined(CONFIG_SOC_NRF52840) - case BIT(2): - if (flags & 0x01) { - mode = RADIO_MODE_MODE_Ble_LR125Kbit; - } else { - mode = RADIO_MODE_MODE_Ble_LR500Kbit; - } - - /* Workaround: nRF52840 Engineering A Errata ID 164 */ - *(volatile u32_t *)0x4000173c |= 0x80000000; - *(volatile u32_t *)0x4000173c = - ((*(volatile u32_t *)0x4000173c) & 0xFFFFFF00) | - 0x5C; - break; -#endif /* CONFIG_SOC_NRF52840 */ -#endif /* CONFIG_SOC_SERIES_NRF52X */ - } + mode = hal_radio_phy_mode_get(phy, flags); NRF_RADIO->MODE = (mode << RADIO_MODE_MODE_Pos) & RADIO_MODE_MODE_Msk; @@ -289,131 +212,22 @@ void radio_pkt_tx_set(void *tx_packet) u32_t radio_tx_ready_delay_get(u8_t phy, u8_t flags) { - /* Return TXEN->TXIDLE + TXIDLE->TX */ - -#if defined(CONFIG_SOC_SERIES_NRF51X) - return 140; -#elif defined(CONFIG_SOC_SERIES_NRF52X) -#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) - return 40; -#elif defined(CONFIG_SOC_NRF52840) - switch (phy) { - default: -#if defined(CONFIG_BT_CTLR_TIFS_HW) - case BIT(0): - return 141; /* floor(140.1 + 1.6) */ - case BIT(1): - return 146; /* floor(145 + 1) */ -#else /* !CONFIG_BT_CTLR_TIFS_HW */ - case BIT(0): - case BIT(1): - return 131; /* floor(129.5 + 1.6) */ -#endif /* !CONFIG_BT_CTLR_TIFS_HW */ - case BIT(2): - if (flags & 0x01) { - return 121; /* floor(119.6 + 2.2) */ - } else { - return 132; /* floor(130 + 2.2) */ - } - } -#else /* !CONFIG_SOC_NRF52840 */ -#if defined(CONFIG_BT_CTLR_TIFS_HW) - return 140; -#else /* !CONFIG_BT_CTLR_TIFS_HW */ - return 131; /* floor(129.5 + 1.6) */ -#endif /* !CONFIG_BT_CTLR_TIFS_HW */ -#endif /* !CONFIG_SOC_NRF52840 */ -#endif /* CONFIG_SOC_SERIES_NRF52X */ + return hal_radio_tx_ready_delay_us_get(phy, flags); } u32_t radio_tx_chain_delay_get(u8_t phy, u8_t flags) { -#if defined(CONFIG_SOC_SERIES_NRF51X) - return 1; /* ceil(1) */ -#elif defined(CONFIG_SOC_SERIES_NRF52X) -#if defined(CONFIG_SOC_NRF52840) - switch (phy) { - default: - case BIT(0): - case BIT(1): - return 1; /* ceil(0.6) */ - case BIT(2): - if (flags & 0x01) { - return 1; /* TODO: different within packet */ - } else { - return 1; /* TODO: different within packet */ - } - } -#else /* !CONFIG_SOC_NRF52840 */ - return 1; /* ceil(0.6) */ -#endif /* !CONFIG_SOC_NRF52840 */ -#endif /* CONFIG_SOC_SERIES_NRF52X */ + return hal_radio_tx_chain_delay_us_get(phy, flags); } -u32_t radio_rx_ready_delay_get(u8_t phy) +u32_t radio_rx_ready_delay_get(u8_t phy, u8_t flags) { - /* Return RXEN->RXIDLE + RXIDLE->RX */ - -#if defined(CONFIG_SOC_SERIES_NRF51X) - return 138; -#elif defined(CONFIG_SOC_SERIES_NRF52X) -#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) - return 40; -#elif defined(CONFIG_SOC_NRF52840) - switch (phy) { - default: -#if defined(CONFIG_BT_CTLR_TIFS_HW) - case BIT(0): - return 141; /* ceil(140.1 + 0.2) */ - case BIT(1): - return 145; /* ceil(144.6 + 0.2) */ -#else /* !CONFIG_BT_CTLR_TIFS_HW */ - case BIT(0): - case BIT(1): - return 130; /* ceil(129.5 + 0.2) */ -#endif /* !CONFIG_BT_CTLR_TIFS_HW */ - case BIT(2): - return 121; /* ceil(120 + 0.2) */ - } -#else /* !CONFIG_SOC_NRF52840 */ -#if defined(CONFIG_BT_CTLR_TIFS_HW) - return 140; -#else /* !CONFIG_BT_CTLR_TIFS_HW */ - return 130; /* ceil(129.5 + 0.2) */ -#endif /* !CONFIG_BT_CTLR_TIFS_HW */ -#endif /* !CONFIG_SOC_NRF52840 */ -#endif /* CONFIG_SOC_SERIES_NRF52X */ + return hal_radio_rx_ready_delay_us_get(phy, flags); } u32_t radio_rx_chain_delay_get(u8_t phy, u8_t flags) { -#if defined(CONFIG_SOC_SERIES_NRF51X) - return 3; /* ceil(3) */ -#elif defined(CONFIG_SOC_SERIES_NRF52X) -#if defined(CONFIG_SOC_NRF52840) - switch (phy) { - default: - case BIT(0): - return 10; /* ceil(9.4) */ - case BIT(1): - return 5; /* ceil(5) */ - case BIT(2): - if (flags & 0x01) { - return 30; /* ceil(29.6) */ - } else { - return 25; /* this is manually measured approx. */ - } - } -#else /* !CONFIG_SOC_NRF52840 */ - switch (phy) { - default: - case BIT(0): - return 10; /* ceil(9.4) */ - case BIT(1): - return 5; /* ceil(5) */ - } -#endif /* !CONFIG_SOC_NRF52840 */ -#endif /* CONFIG_SOC_SERIES_NRF52X */ + return hal_radio_rx_chain_delay_us_get(phy, flags); } void radio_rx_enable(void) @@ -429,9 +243,10 @@ void radio_tx_enable(void) void radio_disable(void) { #if !defined(CONFIG_BT_CTLR_TIFS_HW) - NRF_PPI->CHENCLR = PPI_CHEN_CH7_Msk | PPI_CHEN_CH10_Msk; - NRF_PPI->TASKS_CHG[0].DIS = 1; - NRF_PPI->TASKS_CHG[1].DIS = 1; + NRF_PPI->CHENCLR = HAL_SW_SWITCH_TIMER_CLEAR_PPI_DISABLE | + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_DISABLE; + NRF_PPI->TASKS_CHG[SW_SWITCH_TIMER_TASK_GROUP(0)].DIS = 1; + NRF_PPI->TASKS_CHG[SW_SWITCH_TIMER_TASK_GROUP(1)].DIS = 1; #endif /* !CONFIG_BT_CTLR_TIFS_HW */ NRF_RADIO->SHORTS = 0; @@ -504,99 +319,160 @@ static u8_t sw_tifs_toggle; static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next, u8_t flags_next) { - u8_t ppi = 11 + sw_tifs_toggle; + u8_t ppi = HAL_SW_SWITCH_RADIO_ENABLE_PPI(sw_tifs_toggle); + u8_t cc = SW_SWITCH_TIMER_EVTS_COMP(sw_tifs_toggle); u32_t delay; - NRF_TIMER1->EVENTS_COMPARE[sw_tifs_toggle] = 0; + SW_SWITCH_TIMER->EVENTS_COMPARE[cc] = 0; - NRF_PPI->CH[10].EEP = (u32_t)&(NRF_RADIO->EVENTS_END); - NRF_PPI->CH[10].TEP = (u32_t)&(NRF_PPI->TASKS_CHG[sw_tifs_toggle].EN); + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_EVT = + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT; + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_TASK = + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_TASK(sw_tifs_toggle); + + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(ppi) = + HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(cc); - NRF_PPI->CH[ppi].EEP = (u32_t) - &(NRF_TIMER1->EVENTS_COMPARE[sw_tifs_toggle]); if (dir) { - delay = radio_tx_ready_delay_get(phy_next, flags_next) + - radio_rx_chain_delay_get(phy_curr, 1); + /* TX */ - NRF_PPI->CH[ppi].TEP = (u32_t)&(NRF_RADIO->TASKS_TXEN); + /* Calculate delay with respect to current (RX) and next + * (TX) PHY. If RX PHY is LE Coded, assume S8 coding scheme. + */ + delay = HAL_RADIO_NS2US_ROUND( + hal_radio_tx_ready_delay_ns_get(phy_next, flags_next) + + hal_radio_rx_chain_delay_ns_get(phy_curr, 1)); + + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(ppi) = + HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_TX; #if defined(CONFIG_SOC_NRF52840) if (phy_curr & BIT(2)) { - u8_t ppi_en = 16 + sw_tifs_toggle; - u8_t cc = 2 + sw_tifs_toggle; - u8_t ppi_dis = 8 + sw_tifs_toggle; - u32_t delay; + /* Switching to TX after RX on LE Coded PHY. */ - delay = radio_tx_ready_delay_get(phy_next, flags_next) + - radio_rx_chain_delay_get(phy_curr, 0); + u8_t ppi_en = + HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(sw_tifs_toggle); + u8_t cc_s2 = + SW_SWITCH_TIMER_S2_EVTS_COMP(sw_tifs_toggle); + u8_t ppi_dis = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI( + sw_tifs_toggle); + u32_t delay_s2; - NRF_TIMER1->CC[cc] = NRF_TIMER1->CC[sw_tifs_toggle]; + /* Calculate assuming reception on S2 coding scheme. */ + delay_s2 = HAL_RADIO_NS2US_ROUND( + hal_radio_tx_ready_delay_ns_get( + phy_next, flags_next) + + hal_radio_rx_chain_delay_ns_get(phy_curr, 0)); - if (delay < NRF_TIMER1->CC[cc]) { - NRF_TIMER1->CC[cc] -= delay; + SW_SWITCH_TIMER->CC[cc_s2] = + SW_SWITCH_TIMER->CC[cc]; + + if (delay_s2 < SW_SWITCH_TIMER->CC[cc_s2]) { + SW_SWITCH_TIMER->CC[cc_s2] -= delay_s2; } else { - NRF_TIMER1->CC[cc] = 1; + SW_SWITCH_TIMER->CC[cc_s2] = 1; } - NRF_PPI->CH[ppi_en].EEP = (u32_t) - &(NRF_TIMER1->EVENTS_COMPARE[cc]); - NRF_PPI->CH[ppi_en].TEP = (u32_t) - &(NRF_RADIO->TASKS_TXEN); + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(ppi_en) = + HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(cc_s2); + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(ppi_en) = + HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_TX; - NRF_PPI->CH[ppi_dis].EEP = (u32_t) - &(NRF_TIMER1->EVENTS_COMPARE[cc]); - NRF_PPI->CH[ppi_dis].TEP = (u32_t) - &(NRF_PPI->TASKS_CHG[sw_tifs_toggle].DIS); + /* Wire the Group task disable + * to the S2 EVENTS_COMPARE. + */ + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT( + ppi_dis) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc_s2); - NRF_PPI->CH[18].EEP = (u32_t) - &(NRF_RADIO->EVENTS_RATEBOOST); - NRF_PPI->CH[18].TEP = (u32_t) - &(NRF_TIMER1->TASKS_CAPTURE[sw_tifs_toggle]); + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK( + ppi_dis) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK( + sw_tifs_toggle); - NRF_PPI->CHENSET = PPI_CHEN_CH18_Msk; + /* Capture CC to cancel the timer that has assumed + * S8 reception, if packet will be received in S2. + */ + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT = + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT; + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_TASK = + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK( + sw_tifs_toggle); + + NRF_PPI->CHENSET = + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_ENABLE; } else { - u8_t ppi_en = 16 + sw_tifs_toggle; - u8_t ppi_dis = 8 + sw_tifs_toggle; + /* Switching to TX after RX on LE 1M/2M PHY */ + u8_t ppi_en = + HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(sw_tifs_toggle); + u8_t ppi_dis = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI( + sw_tifs_toggle); - NRF_PPI->CH[ppi_en].EEP = 0; - NRF_PPI->CH[ppi_en].TEP = 0; + /* Invalidate PPI used when RXing on LE Coded PHY. */ + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(ppi_en) + = 0; + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(ppi_en) + = 0; - NRF_PPI->CH[ppi_dis].EEP = (u32_t) - &(NRF_TIMER1->EVENTS_COMPARE[sw_tifs_toggle]); - NRF_PPI->CH[ppi_dis].TEP = (u32_t) - &(NRF_PPI->TASKS_CHG[sw_tifs_toggle].DIS); + /* Wire the Group task disable + * to the default EVENTS_COMPARE. + */ + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT( + ppi_dis) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc); + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK( + ppi_dis) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK( + sw_tifs_toggle); } #endif /* CONFIG_SOC_NRF52840 */ } else { - delay = radio_rx_ready_delay_get(phy_next) - - radio_tx_chain_delay_get(phy_curr, flags_curr) + + /* RX */ + delay = HAL_RADIO_NS2US_CEIL( + hal_radio_rx_ready_delay_ns_get(phy_next, flags_next) - + hal_radio_tx_chain_delay_ns_get(phy_curr, flags_curr)) + 4; /* 4us as +/- active jitter */ - NRF_PPI->CH[ppi].TEP = (u32_t)&(NRF_RADIO->TASKS_RXEN); + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(ppi) = + HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_RX; #if defined(CONFIG_SOC_NRF52840) if (1) { - u8_t ppi_en = 16 + sw_tifs_toggle; - u8_t ppi_dis = 8 + sw_tifs_toggle; + u8_t ppi_en = + HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI( + sw_tifs_toggle); + u8_t ppi_dis = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI( + sw_tifs_toggle); - NRF_PPI->CH[ppi_en].EEP = 0; - NRF_PPI->CH[ppi_en].TEP = 0; + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT( + ppi_en) = 0; + HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK( + ppi_en) = 0; - NRF_PPI->CH[ppi_dis].EEP = (u32_t) - &(NRF_TIMER1->EVENTS_COMPARE[sw_tifs_toggle]); - NRF_PPI->CH[ppi_dis].TEP = (u32_t) - &(NRF_PPI->TASKS_CHG[sw_tifs_toggle].DIS); + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT( + ppi_dis) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc); + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK( + ppi_dis) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK( + sw_tifs_toggle); } #endif /* CONFIG_SOC_NRF52840 */ } - if (delay < NRF_TIMER1->CC[sw_tifs_toggle]) { - NRF_TIMER1->CC[sw_tifs_toggle] -= delay; + if (delay < + SW_SWITCH_TIMER->CC[cc]) { + SW_SWITCH_TIMER->CC[cc] -= delay; } else { - NRF_TIMER1->CC[sw_tifs_toggle] = 1; + SW_SWITCH_TIMER->CC[cc] = 1; } - NRF_PPI->CHENSET = PPI_CHEN_CH7_Msk | PPI_CHEN_CH10_Msk; + NRF_PPI->CHENSET = + HAL_SW_SWITCH_TIMER_CLEAR_PPI_ENABLE | + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_ENABLE; sw_tifs_toggle += 1; sw_tifs_toggle &= 1; @@ -636,7 +512,8 @@ void radio_switch_complete_and_disable(void) (RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk); #if !defined(CONFIG_BT_CTLR_TIFS_HW) - NRF_PPI->CHENCLR = PPI_CHEN_CH7_Msk | PPI_CHEN_CH10_Msk; + NRF_PPI->CHENCLR = HAL_SW_SWITCH_TIMER_CLEAR_PPI_DISABLE | + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_DISABLE; #endif /* !CONFIG_BT_CTLR_TIFS_HW */ } @@ -719,17 +596,19 @@ u32_t radio_bc_has_match(void) void radio_tmr_status_reset(void) { NRF_RTC0->EVTENCLR = RTC_EVTENCLR_COMPARE2_Msk; + + NRF_PPI->CHENCLR = + HAL_RADIO_ENABLE_ON_TICK_PPI_DISABLE | + HAL_EVENT_TIMER_START_PPI_DISABLE | + HAL_RADIO_READY_TIME_CAPTURE_PPI_DISABLE | + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_DISABLE | + HAL_RADIO_DISABLE_ON_HCTO_PPI_DISABLE | + HAL_RADIO_END_TIME_CAPTURE_PPI_DISABLE | #if defined(CONFIG_SOC_NRF52840) - NRF_PPI->CHENCLR = - (PPI_CHEN_CH0_Msk | PPI_CHEN_CH1_Msk | PPI_CHEN_CH2_Msk | - PPI_CHEN_CH3_Msk | PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk | - PPI_CHEN_CH6_Msk | PPI_CHEN_CH13_Msk | PPI_CHEN_CH18_Msk); -#else /* CONFIG_SOC_NRF52840 */ - NRF_PPI->CHENCLR = - (PPI_CHEN_CH0_Msk | PPI_CHEN_CH1_Msk | PPI_CHEN_CH2_Msk | - PPI_CHEN_CH3_Msk | PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk | - PPI_CHEN_CH6_Msk); + HAL_TRIGGER_RATEOVERRIDE_PPI_DISABLE | + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_DISABLE | #endif /* CONFIG_SOC_NRF52840 */ + HAL_TRIGGER_CRYPT_PPI_DISABLE; } void radio_tmr_tifs_set(u32_t tifs) @@ -737,7 +616,7 @@ void radio_tmr_tifs_set(u32_t tifs) #if defined(CONFIG_BT_CTLR_TIFS_HW) NRF_RADIO->TIFS = tifs; #else /* !CONFIG_BT_CTLR_TIFS_HW */ - NRF_TIMER1->CC[sw_tifs_toggle] = tifs; + SW_SWITCH_TIMER->CC[SW_SWITCH_TIMER_EVTS_COMP(sw_tifs_toggle)] = tifs; #endif /* !CONFIG_BT_CTLR_TIFS_HW */ } @@ -749,79 +628,107 @@ u32_t radio_tmr_start(u8_t trx, u32_t ticks_start, u32_t remainder) } remainder /= 1000000UL; - NRF_TIMER0->TASKS_CLEAR = 1; - NRF_TIMER0->MODE = 0; - NRF_TIMER0->PRESCALER = 4; - NRF_TIMER0->BITMODE = 2; /* 24 - bit */ + EVENT_TIMER->TASKS_CLEAR = 1; + EVENT_TIMER->MODE = 0; + EVENT_TIMER->PRESCALER = 4; + EVENT_TIMER->BITMODE = 2; /* 24 - bit */ - NRF_TIMER0->CC[0] = remainder; - NRF_TIMER0->EVENTS_COMPARE[0] = 0; + EVENT_TIMER->CC[0] = remainder; + EVENT_TIMER->EVENTS_COMPARE[0] = 0; NRF_RTC0->CC[2] = ticks_start; NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE2_Msk; NRF_RTC0->EVENTS_COMPARE[2] = 0; - NRF_PPI->CH[1].EEP = (u32_t)&(NRF_RTC0->EVENTS_COMPARE[2]); - NRF_PPI->CH[1].TEP = (u32_t)&(NRF_TIMER0->TASKS_START); - NRF_PPI->CHENSET = PPI_CHEN_CH1_Msk; + HAL_EVENT_TIMER_START_PPI_REGISTER_EVT = HAL_EVENT_TIMER_START_EVT; + HAL_EVENT_TIMER_START_PPI_REGISTER_TASK = HAL_EVENT_TIMER_START_TASK; + NRF_PPI->CHENSET = HAL_EVENT_TIMER_START_PPI_ENABLE; - NRF_PPI->CH[0].EEP = (u32_t)&(NRF_TIMER0->EVENTS_COMPARE[0]); - NRF_PPI->CH[0].TEP = (trx) ? (u32_t)&(NRF_RADIO->TASKS_TXEN) : - (u32_t)&(NRF_RADIO->TASKS_RXEN); - NRF_PPI->CHENSET = PPI_CHEN_CH0_Msk; + HAL_RADIO_ENABLE_ON_TICK_PPI_REGISTER_EVT = + HAL_RADIO_ENABLE_ON_TICK_PPI_EVT; + HAL_RADIO_ENABLE_ON_TICK_PPI_REGISTER_TASK = + (trx) ? HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_TX : + HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_RX; + NRF_PPI->CHENSET = HAL_RADIO_ENABLE_ON_TICK_PPI_ENABLE; #if !defined(CONFIG_BT_CTLR_TIFS_HW) - NRF_TIMER1->TASKS_CLEAR = 1; - NRF_TIMER1->MODE = 0; - NRF_TIMER1->PRESCALER = 4; - NRF_TIMER1->BITMODE = 0; /* 16 bit */ - NRF_TIMER1->TASKS_START = 1; + SW_SWITCH_TIMER->TASKS_CLEAR = 1; + SW_SWITCH_TIMER->MODE = 0; + SW_SWITCH_TIMER->PRESCALER = 4; + SW_SWITCH_TIMER->BITMODE = 0; /* 16 bit */ + SW_SWITCH_TIMER->TASKS_START = 1; - NRF_PPI->CH[7].EEP = (u32_t)&(NRF_RADIO->EVENTS_END); - NRF_PPI->CH[7].TEP = (u32_t)&(NRF_TIMER1->TASKS_CLEAR); + HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_EVT = + HAL_SW_SWITCH_TIMER_CLEAR_PPI_EVT; + HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_TASK = + HAL_SW_SWITCH_TIMER_CLEAR_PPI_TASK; #if defined(CONFIG_SOC_NRF52840) - NRF_PPI->CHG[0] = PPI_CHG_CH8_Msk | PPI_CHG_CH11_Msk | PPI_CHG_CH16_Msk; - NRF_PPI->CHG[1] = PPI_CHG_CH9_Msk | PPI_CHG_CH12_Msk | PPI_CHG_CH17_Msk; + NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(0)] = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE | + HAL_SW_SWITCH_RADIO_ENABLE_PPI_0_INCLUDE | + HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_0_INCLUDE; + NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(1)] = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_1_INCLUDE | + HAL_SW_SWITCH_RADIO_ENABLE_PPI_1_INCLUDE | + HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_1_INCLUDE; #else /* CONFIG_SOC_NRF52840 */ - NRF_PPI->CH[8].EEP = (u32_t)&(NRF_TIMER1->EVENTS_COMPARE[0]); - NRF_PPI->CH[8].TEP = (u32_t)&(NRF_PPI->TASKS_CHG[0].DIS); + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT( + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0)) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT( + SW_SWITCH_TIMER_EVTS_COMP(0)); + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK( + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0)) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(0); - NRF_PPI->CH[9].EEP = (u32_t)&(NRF_TIMER1->EVENTS_COMPARE[1]); - NRF_PPI->CH[9].TEP = (u32_t)&(NRF_PPI->TASKS_CHG[1].DIS); + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT( + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1)) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT( + SW_SWITCH_TIMER_EVTS_COMP(1)); + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK( + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1)) = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(1); - NRF_PPI->CHG[0] = PPI_CHG_CH8_Msk | PPI_CHG_CH11_Msk; - NRF_PPI->CHG[1] = PPI_CHG_CH9_Msk | PPI_CHG_CH12_Msk; + NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(0)] = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE | + HAL_SW_SWITCH_RADIO_ENABLE_PPI_0_INCLUDE; + NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(1)] = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_1_INCLUDE | + HAL_SW_SWITCH_RADIO_ENABLE_PPI_1_INCLUDE; #endif /* CONFIG_SOC_NRF52840 */ #endif /* !CONFIG_BT_CTLR_TIFS_HW */ return remainder; } +static inline void radio_enable_on_timer_tick(u8_t trx) +{ + /* Setup PPI for Radio start */ + HAL_RADIO_ENABLE_ON_TICK_PPI_REGISTER_EVT = + HAL_RADIO_ENABLE_ON_TICK_PPI_EVT; + HAL_RADIO_ENABLE_ON_TICK_PPI_REGISTER_TASK = + (trx) ? HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_TX : + HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_RX; + NRF_PPI->CHENSET = HAL_RADIO_ENABLE_ON_TICK_PPI_ENABLE; +} + void radio_tmr_start_us(u8_t trx, u32_t us) { - NRF_TIMER0->CC[0] = us; - NRF_TIMER0->EVENTS_COMPARE[0] = 0; + EVENT_TIMER->CC[0] = us; + EVENT_TIMER->EVENTS_COMPARE[0] = 0; - NRF_PPI->CH[0].EEP = (u32_t)&(NRF_TIMER0->EVENTS_COMPARE[0]); - NRF_PPI->CH[0].TEP = (trx) ? (u32_t)&(NRF_RADIO->TASKS_TXEN) : - (u32_t)&(NRF_RADIO->TASKS_RXEN); - NRF_PPI->CHENSET = PPI_CHEN_CH0_Msk; + radio_enable_on_timer_tick(trx); } u32_t radio_tmr_start_now(u8_t trx) { u32_t now, start; - /* Setup PPI for Radio start */ - NRF_PPI->CH[0].EEP = (u32_t)&(NRF_TIMER0->EVENTS_COMPARE[0]); - NRF_PPI->CH[0].TEP = (trx) ? (u32_t)&(NRF_RADIO->TASKS_TXEN) : - (u32_t)&(NRF_RADIO->TASKS_RXEN); - NRF_PPI->CHENSET = PPI_CHEN_CH0_Msk; + radio_enable_on_timer_tick(trx); /* Capture the current time */ - NRF_TIMER0->TASKS_CAPTURE[1] = 1; - now = NRF_TIMER0->CC[1]; + EVENT_TIMER->TASKS_CAPTURE[1] = 1; + now = EVENT_TIMER->CC[1]; start = now; /* Setup PPI while determining the latency in doing so */ @@ -830,12 +737,12 @@ u32_t radio_tmr_start_now(u8_t trx) start = (now << 1) - start; /* Setup compare event with min. 1 us offset */ - NRF_TIMER0->CC[0] = start + 1; - NRF_TIMER0->EVENTS_COMPARE[0] = 0; + EVENT_TIMER->CC[0] = start + 1; + EVENT_TIMER->EVENTS_COMPARE[0] = 0; /* Capture the current time */ - NRF_TIMER0->TASKS_CAPTURE[1] = 1; - now = NRF_TIMER0->CC[1]; + EVENT_TIMER->TASKS_CAPTURE[1] = 1; + now = EVENT_TIMER->CC[1]; } while (now > start); return start; @@ -843,39 +750,51 @@ u32_t radio_tmr_start_now(u8_t trx) void radio_tmr_stop(void) { - NRF_TIMER0->TASKS_STOP = 1; - NRF_TIMER0->TASKS_SHUTDOWN = 1; + EVENT_TIMER->TASKS_STOP = 1; + EVENT_TIMER->TASKS_SHUTDOWN = 1; #if !defined(CONFIG_BT_CTLR_TIFS_HW) - NRF_TIMER1->TASKS_STOP = 1; - NRF_TIMER1->TASKS_SHUTDOWN = 1; + SW_SWITCH_TIMER->TASKS_STOP = 1; + SW_SWITCH_TIMER->TASKS_SHUTDOWN = 1; #endif /* !CONFIG_BT_CTLR_TIFS_HW */ } void radio_tmr_hcto_configure(u32_t hcto) { - NRF_TIMER0->CC[1] = hcto; - NRF_TIMER0->EVENTS_COMPARE[1] = 0; + EVENT_TIMER->CC[1] = hcto; + EVENT_TIMER->EVENTS_COMPARE[1] = 0; - NRF_PPI->CH[3].EEP = (u32_t)&(NRF_RADIO->EVENTS_ADDRESS); - NRF_PPI->CH[3].TEP = (u32_t)&(NRF_TIMER0->TASKS_CAPTURE[1]); - NRF_PPI->CH[4].EEP = (u32_t)&(NRF_TIMER0->EVENTS_COMPARE[1]); - NRF_PPI->CH[4].TEP = (u32_t)&(NRF_RADIO->TASKS_DISABLE); - NRF_PPI->CHENSET = (PPI_CHEN_CH3_Msk | PPI_CHEN_CH4_Msk); + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_REGISTER_EVT = + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_EVT; + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_REGISTER_TASK = + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_TASK; + HAL_RADIO_DISABLE_ON_HCTO_PPI_REGISTER_EVT = + HAL_RADIO_DISABLE_ON_HCTO_PPI_EVT; + HAL_RADIO_DISABLE_ON_HCTO_PPI_REGISTER_TASK = + HAL_RADIO_DISABLE_ON_HCTO_PPI_TASK; + NRF_PPI->CHENSET = + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_ENABLE | + HAL_RADIO_DISABLE_ON_HCTO_PPI_ENABLE; } void radio_tmr_aa_capture(void) { - NRF_PPI->CH[2].EEP = (u32_t)&(NRF_RADIO->EVENTS_READY); - NRF_PPI->CH[2].TEP = (u32_t)&(NRF_TIMER0->TASKS_CAPTURE[0]); - NRF_PPI->CH[3].EEP = (u32_t)&(NRF_RADIO->EVENTS_ADDRESS); - NRF_PPI->CH[3].TEP = (u32_t)&(NRF_TIMER0->TASKS_CAPTURE[1]); - NRF_PPI->CHENSET = (PPI_CHEN_CH2_Msk | PPI_CHEN_CH3_Msk); + HAL_RADIO_READY_TIME_CAPTURE_PPI_REGISTER_EVT = + HAL_RADIO_READY_TIME_CAPTURE_PPI_EVT; + HAL_RADIO_READY_TIME_CAPTURE_PPI_REGISTER_TASK = + HAL_RADIO_READY_TIME_CAPTURE_PPI_TASK; + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_REGISTER_EVT = + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_EVT; + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_REGISTER_TASK = + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_TASK; + NRF_PPI->CHENSET = + HAL_RADIO_READY_TIME_CAPTURE_PPI_ENABLE | + HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_ENABLE; } u32_t radio_tmr_aa_get(void) { - return NRF_TIMER0->CC[1]; + return EVENT_TIMER->CC[1]; } static u32_t radio_tmr_aa; @@ -893,29 +812,31 @@ u32_t radio_tmr_aa_restore(void) u32_t radio_tmr_ready_get(void) { - return NRF_TIMER0->CC[0]; + return EVENT_TIMER->CC[0]; } void radio_tmr_end_capture(void) { - NRF_PPI->CH[5].EEP = (u32_t)&(NRF_RADIO->EVENTS_END); - NRF_PPI->CH[5].TEP = (u32_t)&(NRF_TIMER0->TASKS_CAPTURE[2]); - NRF_PPI->CHENSET = PPI_CHEN_CH5_Msk; + HAL_RADIO_END_TIME_CAPTURE_PPI_REGISTER_EVT = + HAL_RADIO_END_TIME_CAPTURE_PPI_EVT; + HAL_RADIO_END_TIME_CAPTURE_PPI_REGISTER_TASK = + HAL_RADIO_END_TIME_CAPTURE_PPI_TASK; + NRF_PPI->CHENSET = HAL_RADIO_END_TIME_CAPTURE_PPI_ENABLE; } u32_t radio_tmr_end_get(void) { - return NRF_TIMER0->CC[2]; + return EVENT_TIMER->CC[2]; } void radio_tmr_sample(void) { - NRF_TIMER0->TASKS_CAPTURE[3] = 1; + EVENT_TIMER->TASKS_CAPTURE[3] = 1; } u32_t radio_tmr_sample_get(void) { - return NRF_TIMER0->CC[3]; + return EVENT_TIMER->CC[3]; } #if defined(CONFIG_BT_CTLR_GPIO_PA_PIN) || \ @@ -980,23 +901,24 @@ void radio_gpio_lna_off(void) void radio_gpio_pa_lna_enable(u32_t trx_us) { - NRF_TIMER0->CC[2] = trx_us; - NRF_TIMER0->EVENTS_COMPARE[2] = 0; + EVENT_TIMER->CC[2] = trx_us; + EVENT_TIMER->EVENTS_COMPARE[2] = 0; - NRF_PPI->CH[14].EEP = (u32_t)&(NRF_TIMER0->EVENTS_COMPARE[2]); - NRF_PPI->CH[14].TEP = (u32_t) - &(NRF_GPIOTE->TASKS_OUT[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN]); + HAL_ENABLE_PALNA_PPI_REGISTER_EVT = HAL_ENABLE_PALNA_PPI_EVT; + HAL_ENABLE_PALNA_PPI_REGISTER_TASK = HAL_ENABLE_PALNA_PPI_TASK; - NRF_PPI->CH[15].EEP = (u32_t)&(NRF_RADIO->EVENTS_DISABLED); - NRF_PPI->CH[15].TEP = (u32_t) - &(NRF_GPIOTE->TASKS_OUT[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN]); + HAL_DISABLE_PALNA_PPI_REGISTER_EVT = HAL_DISABLE_PALNA_PPI_EVT; + HAL_DISABLE_PALNA_PPI_REGISTER_TASK = HAL_DISABLE_PALNA_PPI_TASK; - NRF_PPI->CHENSET = PPI_CHEN_CH14_Msk | PPI_CHEN_CH15_Msk; + NRF_PPI->CHENSET = + HAL_ENABLE_PALNA_PPI_ENABLE | HAL_DISABLE_PALNA_PPI_ENABLE; } void radio_gpio_pa_lna_disable(void) { - NRF_PPI->CHENCLR = PPI_CHEN_CH14_Msk | PPI_CHEN_CH15_Msk; + NRF_PPI->CHENCLR = + HAL_ENABLE_PALNA_PPI_DISABLE | + HAL_DISABLE_PALNA_PPI_DISABLE; } #endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */ @@ -1041,9 +963,11 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt) CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) & CCM_RATEOVERRIDE_RATEOVERRIDE_Msk; - NRF_PPI->CH[13].EEP = (u32_t)&(NRF_RADIO->EVENTS_RATEBOOST); - NRF_PPI->CH[13].TEP = (u32_t)&(NRF_CCM->TASKS_RATEOVERRIDE); - NRF_PPI->CHENSET = PPI_CHEN_CH13_Msk; + HAL_TRIGGER_RATEOVERRIDE_PPI_REGISTER_EVT = + HAL_TRIGGER_RATEOVERRIDE_PPI_EVT; + HAL_TRIGGER_RATEOVERRIDE_PPI_REGISTER_TASK = + HAL_TRIGGER_RATEOVERRIDE_PPI_TASK; + NRF_PPI->CHENSET = HAL_TRIGGER_RATEOVERRIDE_PPI_ENABLE; break; #endif /* CONFIG_SOC_NRF52840 */ } @@ -1058,9 +982,9 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt) NRF_CCM->EVENTS_ENDCRYPT = 0; NRF_CCM->EVENTS_ERROR = 0; - NRF_PPI->CH[6].EEP = (u32_t)&(NRF_RADIO->EVENTS_ADDRESS); - NRF_PPI->CH[6].TEP = (u32_t)&(NRF_CCM->TASKS_CRYPT); - NRF_PPI->CHENSET = PPI_CHEN_CH6_Msk; + HAL_TRIGGER_CRYPT_PPI_REGISTER_EVT = HAL_TRIGGER_CRYPT_PPI_EVT; + HAL_TRIGGER_CRYPT_PPI_REGISTER_TASK = HAL_TRIGGER_CRYPT_PPI_TASK; + NRF_PPI->CHENSET = HAL_TRIGGER_CRYPT_PPI_ENABLE; NRF_CCM->TASKS_KSGEN = 1; @@ -1138,9 +1062,9 @@ void radio_ar_configure(u32_t nirk, void *irk) radio_bc_configure(64); radio_bc_status_reset(); - NRF_PPI->CH[6].EEP = (u32_t)&(NRF_RADIO->EVENTS_BCMATCH); - NRF_PPI->CH[6].TEP = (u32_t)&(NRF_AAR->TASKS_START); - NRF_PPI->CHENSET = PPI_CHEN_CH6_Msk; + HAL_TRIGGER_AAR_PPI_REGISTER_EVT = HAL_TRIGGER_AAR_PPI_EVT; + HAL_TRIGGER_AAR_PPI_REGISTER_TASK = HAL_TRIGGER_AAR_PPI_TASK; + NRF_PPI->CHENSET = HAL_TRIGGER_AAR_PPI_ENABLE; } u32_t radio_ar_match_get(void) diff --git a/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf5.h b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf5.h new file mode 100644 index 00000000000..4044e8e5f1b --- /dev/null +++ b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf5.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2018 Ioannis Glaropoulos + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define HAL_RADIO_NS2US_CEIL(ns) ((ns + 999)/1000) +#define HAL_RADIO_NS2US_ROUND(ns) ((ns + 500)/1000) + +#define EVENT_TIMER NRF_TIMER0 + +#if defined(CONFIG_SOC_SERIES_NRF51X) +#include "radio_nrf51.h" +#elif defined(CONFIG_SOC_NRF52832) +#include "radio_nrf52832.h" +#elif defined(CONFIG_SOC_NRF52840) +#include "radio_nrf52840.h" +#endif + +#include "radio_nrf5_ppi.h" diff --git a/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf51.h b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf51.h new file mode 100644 index 00000000000..82205b7d618 --- /dev/null +++ b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf51.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2018 Ioannis Glaropoulos + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if !defined(CONFIG_BT_CTLR_TIFS_HW) +#define SW_SWITCH_TIMER NRF_TIMER1 +#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0 +#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0 +#endif + +/* TXEN->TXIDLE + TXIDLE->TX in microseconds. */ +#define HAL_RADIO_NRF51_TXEN_TXIDLE_TX_US 140 +#define HAL_RADIO_NRF51_TXEN_TXIDLE_TX_NS 140000 +/* RXEN->RXIDLE + RXIDLE->RX in microseconds. */ +#define HAL_RADIO_NRF51_RXEN_RXIDLE_RX_US 138 +#define HAL_RADIO_NRF51_RXEN_RXIDLE_RX_NS 138000 + +#define HAL_RADIO_NRF51_TX_CHAIN_DELAY_US 1 /* ceil(1.0) */ +#define HAL_RADIO_NRF51_TX_CHAIN_DELAY_NS 1000 /* 1.0 */ +#define HAL_RADIO_NRF51_RX_CHAIN_DELAY_US 3 /* ceil(3.0) */ +#define HAL_RADIO_NRF51_RX_CHAIN_DELAY_NS 3000 /* 3.0 */ + +static inline void hal_radio_ram_prio_setup(void) +{ +} + +static inline u32_t hal_radio_phy_mode_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(flags); + u32_t mode; + + switch (phy) { + case BIT(0): + default: + mode = RADIO_MODE_MODE_Ble_1Mbit; + break; + + case BIT(1): + mode = RADIO_MODE_MODE_Nrf_2Mbit; + break; + } + + return mode; +} + +static inline u32_t hal_radio_tx_ready_delay_us_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + return HAL_RADIO_NRF51_TXEN_TXIDLE_TX_US; +} + +static inline u32_t hal_radio_rx_ready_delay_us_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + return HAL_RADIO_NRF51_RXEN_RXIDLE_RX_US; +} + +static inline u32_t hal_radio_tx_chain_delay_us_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + return HAL_RADIO_NRF51_TX_CHAIN_DELAY_US; +} + +static inline u32_t hal_radio_rx_chain_delay_us_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + return HAL_RADIO_NRF51_RX_CHAIN_DELAY_US; +} + +static inline u32_t hal_radio_tx_ready_delay_ns_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + return HAL_RADIO_NRF51_TXEN_TXIDLE_TX_NS; +} + +static inline u32_t hal_radio_rx_ready_delay_ns_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + return HAL_RADIO_NRF51_RXEN_RXIDLE_RX_NS; +} + +static inline u32_t hal_radio_tx_chain_delay_ns_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + return HAL_RADIO_NRF51_TX_CHAIN_DELAY_NS; +} + +static inline u32_t hal_radio_rx_chain_delay_ns_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + return HAL_RADIO_NRF51_RX_CHAIN_DELAY_NS; +} diff --git a/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf52832.h b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf52832.h new file mode 100644 index 00000000000..29f299ae8ef --- /dev/null +++ b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf52832.h @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2018 Ioannis Glaropoulos + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if !defined(CONFIG_BT_CTLR_TIFS_HW) +#define SW_SWITCH_TIMER NRF_TIMER1 +#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0 +#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0 +#endif + +/* NRF Radio HW timing constants + * - provided in US and NS (for higher granularity) + * - based on empirical measurements and sniffer logs + */ + +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE 1M PHY. + */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_FAST_NS 41050 /* 40.1 + 0.95 */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_FAST_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 1M PHY. + */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_NS 141050 /*140.1 + 0.95*/ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode + * and no HW TIFS auto-switch) in microseconds for LE 1M PHY. + */ +/* 129 + 0.95 */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS 129950 +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE 2M PHY. + */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_FAST_NS 40000 /* 40.1 - 0.1 */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_FAST_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY. + */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_NS 144500 /* 144.6 - 0.1 */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode + * and no HW TIFS auto-switch) in microseconds for LE 2M PHY. + */ +/* 129 - 0.1 */ +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS 128900 +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE 1M PHY. + */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_FAST_NS 40300 /* 40.1 + 0.2 */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE 1M PHY. + */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_NS 140300 /*140.1 + 0.2*/ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 1M PHY. + */ +/* 129 + 0.2 */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS 129200 +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE 2M PHY. + */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_FAST_NS 40300 /* 40.1 + 0.2 */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY. + */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_NS 144800 /* 144.6 + 0.2 */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY. + */ +/* 129 + 0.2 */ +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS 129200 +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL(\ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS) + +#define HAL_RADIO_NRF52832_TX_CHAIN_DELAY_NS 600 /* 0.6 */ +#define HAL_RADIO_NRF52832_TX_CHAIN_DELAY_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52832_TX_CHAIN_DELAY_NS) + +#define HAL_RADIO_NRF52832_RX_CHAIN_DELAY_1M_NS 9400 /* 9.4 */ +#define HAL_RADIO_NRF52832_RX_CHAIN_DELAY_1M_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52832_RX_CHAIN_DELAY_1M_NS) + +#define HAL_RADIO_NRF52832_RX_CHAIN_DELAY_2M_NS 5450 /* 5.0 + 0.45 */ +#define HAL_RADIO_NRF52832_RX_CHAIN_DELAY_2M_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52832_RX_CHAIN_DELAY_2M_NS) + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_US \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_FAST_US +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_NS \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_US \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_US +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_NS \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_NS +#else +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_US \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_NS \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_US \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_FAST_US +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_NS \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_US \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_US +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_NS \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_NS +#else +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_US \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_NS \ + HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_US \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_FAST_US +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_NS \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_US \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_US +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_NS \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_NS +#else +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_US \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_NS \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_US \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_FAST_US +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_NS \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_US \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_US +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_NS \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_NS +#else +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_US \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_NS \ + HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +static inline void hal_radio_ram_prio_setup(void) +{ + struct { + u32_t volatile reserved_0[0x5a0 >> 2]; + u32_t volatile bridge_type; + u32_t volatile reserved_1[((0xe00 - 0x5a0) >> 2) - 1]; + struct { + u32_t volatile CPU0; + u32_t volatile SPIS1; + u32_t volatile RADIO; + u32_t volatile ECB; + u32_t volatile CCM; + u32_t volatile AAR; + u32_t volatile SAADC; + u32_t volatile UARTE; + u32_t volatile SERIAL0; + u32_t volatile SERIAL2; + u32_t volatile NFCT; + u32_t volatile I2S; + u32_t volatile PDM; + u32_t volatile PWM; + } RAMPRI; + } volatile *NRF_AMLI = (void volatile *)0x40000000UL; + + NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.SPIS1 = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.RADIO = 0x00000000UL; + NRF_AMLI->RAMPRI.ECB = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.CCM = 0x00000000UL; + NRF_AMLI->RAMPRI.AAR = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.SAADC = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.UARTE = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.SERIAL0 = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.SERIAL2 = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.NFCT = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.I2S = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.PDM = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.PWM = 0xFFFFFFFFUL; +} + +static inline u32_t hal_radio_phy_mode_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(flags); + u32_t mode; + + switch (phy) { + case BIT(0): + default: + mode = RADIO_MODE_MODE_Ble_1Mbit; + break; + + case BIT(1): + mode = RADIO_MODE_MODE_Ble_2Mbit; + break; + } + + return mode; +} + +static inline u32_t hal_radio_tx_ready_delay_us_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(flags); + + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_US; + case BIT(1): + return HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_US; + } +} + +static inline u32_t hal_radio_rx_ready_delay_us_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(flags); + + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_US; + case BIT(1): + return HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_US; + } +} + +static inline u32_t hal_radio_tx_chain_delay_us_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + + return HAL_RADIO_NRF52832_TX_CHAIN_DELAY_US; +} + +static inline u32_t hal_radio_rx_chain_delay_us_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(flags); + + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52832_RX_CHAIN_DELAY_1M_US; + case BIT(1): + return HAL_RADIO_NRF52832_RX_CHAIN_DELAY_2M_US; + } +} + +static inline u32_t hal_radio_tx_ready_delay_ns_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(flags); + + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_1M_NS; + case BIT(1): + return HAL_RADIO_NRF52832_TXEN_TXIDLE_TX_2M_NS; + } +} + +static inline u32_t hal_radio_rx_ready_delay_ns_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(flags); + + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_1M_NS; + case BIT(1): + return HAL_RADIO_NRF52832_RXEN_RXIDLE_RX_2M_NS; + } +} + +static inline u32_t hal_radio_tx_chain_delay_ns_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(phy); + ARG_UNUSED(flags); + + return HAL_RADIO_NRF52832_TX_CHAIN_DELAY_US; +} + +static inline u32_t hal_radio_rx_chain_delay_ns_get(u8_t phy, u8_t flags) +{ + ARG_UNUSED(flags); + + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52832_RX_CHAIN_DELAY_1M_NS; + case BIT(1): + return HAL_RADIO_NRF52832_RX_CHAIN_DELAY_2M_NS; + } +} diff --git a/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf52840.h b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf52840.h new file mode 100644 index 00000000000..2813017c2b4 --- /dev/null +++ b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf52840.h @@ -0,0 +1,582 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2018 Ioannis Glaropoulos + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if !defined(CONFIG_BT_CTLR_TIFS_HW) +#define SW_SWITCH_TIMER NRF_TIMER1 +#define SW_SWITCH_TIMER_EVTS_COMP_BASE 0 +#define SW_SWITCH_TIMER_EVTS_COMP_S2_BASE 2 +#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0 +#endif + +/* NRF Radio HW timing constants + * - provided in US and NS (for higher granularity) + * - based on empirical measurements and sniffer logs + */ + +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE 1M PHY. + */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_FAST_NS 40900 /*40.1 + 0.8*/ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_FAST_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 1M PHY. + */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_NS 140900 /*140.1 + 0.8*/ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode + * and no HW TIFS auto-switch) in microseconds for LE 1M PHY. + */ + /* 129.5 + 0.8 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS 130300 +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE 2M PHY. + */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_FAST_NS 40000 /* 40.1 - 0.1 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_FAST_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY. + */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_NS 144900 /* 145 - 0.1 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY. + */ +/* 129.5 - 0.1 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS 129400 +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE CODED PHY [S2]. + */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_FAST_NS 42300 /* 40.1 + 2.2 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_FAST_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY [S2]. + */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_NS 132200 /* 130 + 2.2 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S2]. + */ +/* 129.5 + 2.2 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS 131700 +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE CODED PHY [S8]. + */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_FAST_NS 42300 /* 40.1 + 2.2 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_FAST_NS) +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY [S8]. + */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_NS 121800 /*119.6 + 2.2*/ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S8]. + */ + /* 129.5 + 2.2 */ +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS 131700 +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE 1M PHY. + */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_FAST_NS 40300 /* 40.1 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE 1M PHY. + */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_NS 140300 /*140.1 + 0.2*/ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 1M PHY. + */ +/* 129.5 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS 129700 +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE 2M PHY. + */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_FAST_NS 40300 /* 40.1 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY. + */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_NS 144800 /*144.6 + 0.2*/ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY. + */ +/* 129.5 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS 129700 +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE Coded PHY [S2]. + */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_FAST_NS 40300 /* 40.1 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE Coded PHY [S2]. + */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_NS 130200 /* 130 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode + * and no HW TIFS auto-switch) in microseconds for LE Coded PHY [S2]. + */ +/* 129.5 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS 129700 +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE Coded PHY [S8]. + */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_FAST_NS 40300 /* 40.1 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE Coded PHY [S8]. + */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_NS 120200 /* 120.0 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE Coded PHY [S8]. + */ +/* 129.5 + 0.2 */ +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS 129700 +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS) + +#define HAL_RADIO_NRF52840_TX_CHAIN_DELAY_1M_US 1 /* ceil(0.6) */ +#define HAL_RADIO_NRF52840_TX_CHAIN_DELAY_1M_NS 600 /* 0.6 */ +#define HAL_RADIO_NRF52840_TX_CHAIN_DELAY_2M_US 1 /* ceil(0.6) */ +#define HAL_RADIO_NRF52840_TX_CHAIN_DELAY_2M_NS 600 /* 0.6 */ +#define HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S2_US 6 /* ceil(6.0) */ +#define HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S2_NS 6000 /* 6.0 */ +#define HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S8_US 6 /* ceil(6.0) */ +#define HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S8_NS 6000 /* 6.0 */ + +#define HAL_RADIO_NRF52840_RX_CHAIN_DELAY_1M_US 10 /* ceil(9.4) */ +#define HAL_RADIO_NRF52840_RX_CHAIN_DELAY_1M_NS 9400 /* 9.4 */ +#define HAL_RADIO_NRF52840_RX_CHAIN_DELAY_2M_US 5 /* ceil(5.0) */ +#define HAL_RADIO_NRF52840_RX_CHAIN_DELAY_2M_NS 5000 /* 5.0 */ +#define HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S2_US 20 /* ceil(19.6) */ +#define HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S2_NS 19600 /* 19.6 */ +#define HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S8_US 30 /* ceil(29.6) */ +#define HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S8_NS 29600 /* 29.6 */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_FAST_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_NS +#else +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_FAST_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_NS +#else +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_FAST_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_NS +#else +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_FAST_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_NS +#else +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_FAST_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_NS +#else +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_FAST_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_NS +#else +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_FAST_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_NS +#else +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +#if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_FAST_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_FAST_NS +#else +#if defined(CONFIG_BT_CTLR_TIFS_HW) +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_NS +#else +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS +#endif /* CONFIG_BT_CTLR_TIFS_HW */ +#endif /* CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ + +static inline void hal_radio_ram_prio_setup(void) +{ + struct { + u32_t volatile reserved_0[0x5a0 >> 2]; + u32_t volatile bridge_type; + u32_t volatile reserved_1[((0xe00 - 0x5a0) >> 2) - 1]; + struct { + u32_t volatile CPU0; + u32_t volatile SPIS1; + u32_t volatile RADIO; + u32_t volatile ECB; + u32_t volatile CCM; + u32_t volatile AAR; + u32_t volatile SAADC; + u32_t volatile UARTE; + u32_t volatile SERIAL0; + u32_t volatile SERIAL2; + u32_t volatile NFCT; + u32_t volatile I2S; + u32_t volatile PDM; + u32_t volatile PWM; + } RAMPRI; + } volatile *NRF_AMLI = (void volatile *)0x40000000UL; + + NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.SPIS1 = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.RADIO = 0x00000000UL; + NRF_AMLI->RAMPRI.ECB = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.CCM = 0x00000000UL; + NRF_AMLI->RAMPRI.AAR = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.SAADC = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.UARTE = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.SERIAL0 = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.SERIAL2 = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.NFCT = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.I2S = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.PDM = 0xFFFFFFFFUL; + NRF_AMLI->RAMPRI.PWM = 0xFFFFFFFFUL; +} + +static inline u32_t hal_radio_phy_mode_get(u8_t phy, u8_t flags) +{ + u32_t mode; + + switch (phy) { + case BIT(0): + default: + mode = RADIO_MODE_MODE_Ble_1Mbit; + /* Workaround: nRF52840 Engineering A Errata ID 164 */ + *(volatile u32_t *)0x4000173c &= ~0x80000000; + break; + + case BIT(1): + /* Workaround: nRF52840 Engineering A Errata ID 164 */ + *(volatile u32_t *)0x4000173c &= ~0x80000000; + mode = RADIO_MODE_MODE_Ble_2Mbit; + break; + + case BIT(2): + if (flags & 0x01) { + mode = RADIO_MODE_MODE_Ble_LR125Kbit; + } else { + mode = RADIO_MODE_MODE_Ble_LR500Kbit; + } + /* Workaround: nRF52840 Engineering A Errata ID 164 */ + *(volatile u32_t *)0x4000173c |= 0x80000000; + *(volatile u32_t *)0x4000173c = + ((*(volatile u32_t *)0x4000173c) & 0xFFFFFF00) | + 0x5C; + break; + } + + return mode; +} + +static inline u32_t hal_radio_tx_ready_delay_us_get(u8_t phy, u8_t flags) +{ + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_US; + case BIT(1): + return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_US; + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_US; + } else { + return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_US; + } + } +} + +static inline u32_t hal_radio_rx_ready_delay_us_get(u8_t phy, u8_t flags) +{ + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_US; + case BIT(1): + return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_US; + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_US; + } else { + return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_US; + } + } +} + +static inline u32_t hal_radio_tx_chain_delay_us_get(u8_t phy, u8_t flags) +{ + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_1M_US; + case BIT(1): + return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_2M_US; + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S8_US; + } else { + return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S2_US; + } + } +} + +static inline u32_t hal_radio_rx_chain_delay_us_get(u8_t phy, u8_t flags) +{ + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_1M_US; + case BIT(1): + return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_2M_US; + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S8_US; + } else { + return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S2_US; + } + } +} + +static inline u32_t hal_radio_tx_ready_delay_ns_get(u8_t phy, u8_t flags) +{ + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_NS; + case BIT(1): + return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_NS; + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_NS; + } else { + return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_NS; + } + } +} + +static inline u32_t hal_radio_rx_ready_delay_ns_get(u8_t phy, u8_t flags) +{ + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_NS; + case BIT(1): + return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_NS; + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_NS; + } else { + return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_NS; + } + } +} + +static inline u32_t hal_radio_tx_chain_delay_ns_get(u8_t phy, u8_t flags) +{ + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_1M_NS; + case BIT(1): + return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_2M_NS; + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S8_NS; + } else { + return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S2_NS; + } + } +} + +static inline u32_t hal_radio_rx_chain_delay_ns_get(u8_t phy, u8_t flags) +{ + switch (phy) { + default: + case BIT(0): + return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_1M_NS; + case BIT(1): + return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_2M_NS; + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S8_NS; + } else { + return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S2_NS; + } + } +} diff --git a/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf5_ppi.h b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf5_ppi.h new file mode 100644 index 00000000000..f43dbfd9353 --- /dev/null +++ b/subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf5_ppi.h @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2018 Ioannis Glaropoulos + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X) + +/* Enable Radio on Event Timer tick: + * wire the EVENT_TIMER EVENTS_COMPARE[0] event to RADIO TASKS_TXEN/RXEN task. + */ +#define HAL_RADIO_ENABLE_ON_TICK_PPI 0 +#define HAL_RADIO_ENABLE_ON_TICK_PPI_ENABLE \ + ((PPI_CHENSET_CH0_Set << PPI_CHENSET_CH0_Pos) & PPI_CHENSET_CH0_Msk) +#define HAL_RADIO_ENABLE_ON_TICK_PPI_DISABLE \ + ((PPI_CHENCLR_CH0_Clear << PPI_CHENCLR_CH0_Pos) & PPI_CHENCLR_CH0_Msk) +#define HAL_RADIO_ENABLE_ON_TICK_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_RADIO_ENABLE_ON_TICK_PPI].EEP +#define HAL_RADIO_ENABLE_ON_TICK_PPI_EVT \ + ((u32_t)&(EVENT_TIMER->EVENTS_COMPARE[0])) +#define HAL_RADIO_ENABLE_ON_TICK_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_RADIO_ENABLE_ON_TICK_PPI].TEP +#define HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_TX \ + ((u32_t)&(NRF_RADIO->TASKS_TXEN)) +#define HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_RX \ + ((u32_t)&(NRF_RADIO->TASKS_RXEN)) + +/* Start event timer on RTC tick: + * wire the RTC0 EVENTS_COMPARE[2] event to EVENT_TIMER TASKS_START task. + */ +#define HAL_EVENT_TIMER_START_PPI 1 +#define HAL_EVENT_TIMER_START_PPI_ENABLE \ + ((PPI_CHENSET_CH1_Set << PPI_CHENSET_CH1_Pos) & PPI_CHENSET_CH1_Msk) +#define HAL_EVENT_TIMER_START_PPI_DISABLE \ + ((PPI_CHENCLR_CH1_Clear << PPI_CHENCLR_CH1_Pos) & PPI_CHENCLR_CH1_Msk) +#define HAL_EVENT_TIMER_START_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_EVENT_TIMER_START_PPI].EEP +#define HAL_EVENT_TIMER_START_EVT \ + ((u32_t)&(NRF_RTC0->EVENTS_COMPARE[2])) +#define HAL_EVENT_TIMER_START_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_EVENT_TIMER_START_PPI].TEP +#define HAL_EVENT_TIMER_START_TASK \ + ((u32_t)&(EVENT_TIMER->TASKS_START)) + +/* Capture event timer on Radio ready: + * wire the RADIO EVENTS_READY event to the + * EVENT_TIMER TASKS_CAPTURE[] task. + */ +#define HAL_RADIO_READY_TIME_CAPTURE_PPI 2 +#define HAL_RADIO_READY_TIME_CAPTURE_PPI_ENABLE \ + ((PPI_CHENSET_CH2_Set << PPI_CHENSET_CH2_Pos) & PPI_CHENSET_CH2_Msk) +#define HAL_RADIO_READY_TIME_CAPTURE_PPI_DISABLE \ + ((PPI_CHENCLR_CH2_Clear << PPI_CHENCLR_CH2_Pos) & PPI_CHENCLR_CH2_Msk) +#define HAL_RADIO_READY_TIME_CAPTURE_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_RADIO_READY_TIME_CAPTURE_PPI].EEP +#define HAL_RADIO_READY_TIME_CAPTURE_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_READY)) +#define HAL_RADIO_READY_TIME_CAPTURE_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_RADIO_READY_TIME_CAPTURE_PPI].TEP +#define HAL_RADIO_READY_TIME_CAPTURE_PPI_TASK \ + ((u32_t)&(EVENT_TIMER->TASKS_CAPTURE[0])) + +/* Capture event timer on Address reception: + * wire the RADIO EVENTS_ADDRESS event to the + * EVENT_TIMER TASKS_CAPTURE[
] task. + */ +#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 3 +#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_ENABLE \ + ((PPI_CHENSET_CH3_Set << PPI_CHENSET_CH3_Pos) & PPI_CHENSET_CH3_Msk) +#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_DISABLE \ + ((PPI_CHENCLR_CH3_Clear << PPI_CHENCLR_CH3_Pos) & PPI_CHENCLR_CH3_Msk) +#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI].EEP +#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_ADDRESS)) +#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI].TEP +#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_TASK \ + ((u32_t)&(EVENT_TIMER->TASKS_CAPTURE[1])) + +/* Disable Radio on HCTO: + * wire the EVENT_TIMER EVENTS_COMPARE[] event + * to the RADIO TASKS_DISABLE task. + */ +#define HAL_RADIO_DISABLE_ON_HCTO_PPI 4 +#define HAL_RADIO_DISABLE_ON_HCTO_PPI_ENABLE \ + ((PPI_CHENSET_CH4_Set << PPI_CHENSET_CH4_Pos) & PPI_CHENSET_CH4_Msk) +#define HAL_RADIO_DISABLE_ON_HCTO_PPI_DISABLE \ + ((PPI_CHENCLR_CH4_Clear << PPI_CHENCLR_CH4_Pos) & PPI_CHENCLR_CH4_Msk) +#define HAL_RADIO_DISABLE_ON_HCTO_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_RADIO_DISABLE_ON_HCTO_PPI].EEP +#define HAL_RADIO_DISABLE_ON_HCTO_PPI_EVT \ + ((u32_t)&(EVENT_TIMER->EVENTS_COMPARE[1])) +#define HAL_RADIO_DISABLE_ON_HCTO_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_RADIO_DISABLE_ON_HCTO_PPI].TEP +#define HAL_RADIO_DISABLE_ON_HCTO_PPI_TASK \ + ((u32_t)&(NRF_RADIO->TASKS_DISABLE)) + +/* Capture event timer on Radio end: + * wire the RADIO EVENTS_END event to the + * EVENT_TIMER TASKS_CAPTURE[] task. + */ +#define HAL_RADIO_END_TIME_CAPTURE_PPI 5 +#define HAL_RADIO_END_TIME_CAPTURE_PPI_ENABLE \ + ((PPI_CHENSET_CH5_Set << PPI_CHENSET_CH5_Pos) & PPI_CHENSET_CH5_Msk) +#define HAL_RADIO_END_TIME_CAPTURE_PPI_DISABLE \ + ((PPI_CHENCLR_CH5_Clear << PPI_CHENCLR_CH5_Pos) & PPI_CHENCLR_CH5_Msk) +#define HAL_RADIO_END_TIME_CAPTURE_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_RADIO_END_TIME_CAPTURE_PPI].EEP +#define HAL_RADIO_END_TIME_CAPTURE_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_END)) +#define HAL_RADIO_END_TIME_CAPTURE_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_RADIO_END_TIME_CAPTURE_PPI].TEP +#define HAL_RADIO_END_TIME_CAPTURE_PPI_TASK \ + ((u32_t)&(EVENT_TIMER->TASKS_CAPTURE[2])) + +/* Trigger encryption task upon Address reception: + * wire the RADIO EVENTS_ADDRESS event to the CCM TASKS_CRYPT task. + */ +#define HAL_TRIGGER_CRYPT_PPI 6 +#define HAL_TRIGGER_CRYPT_PPI_ENABLE \ + ((PPI_CHENSET_CH6_Set << PPI_CHENSET_CH6_Pos) & PPI_CHENSET_CH6_Msk) +#define HAL_TRIGGER_CRYPT_PPI_DISABLE \ + ((PPI_CHENCLR_CH6_Clear << PPI_CHENCLR_CH6_Pos) & PPI_CHENCLR_CH6_Msk) +#define HAL_TRIGGER_CRYPT_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_TRIGGER_CRYPT_PPI].EEP +#define HAL_TRIGGER_CRYPT_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_ADDRESS)) +#define HAL_TRIGGER_CRYPT_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_TRIGGER_CRYPT_PPI].TEP +#define HAL_TRIGGER_CRYPT_PPI_TASK \ + ((u32_t)&(NRF_CCM->TASKS_CRYPT)) + +/* Trigger automatic address resolution on Bit counter match: + * wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task. + * Note that this PPI channel is shared with the encrypt triggering on Address + * reception. + */ +#define HAL_TRIGGER_AAR_PPI 6 +#define HAL_TRIGGER_AAR_PPI_ENABLE \ + ((PPI_CHENSET_CH6_Set << PPI_CHENSET_CH6_Pos) & PPI_CHENSET_CH6_Msk) +#define HAL_TRIGGER_AAR_PPI_DISABLE \ + ((PPI_CHENCLR_CH6_Clear << PPI_CHENCLR_CH6_Pos) & PPI_CHENCLR_CH6_Msk) +#define HAL_TRIGGER_AAR_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_TRIGGER_AAR_PPI].EEP +#define HAL_TRIGGER_AAR_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_BCMATCH)) +#define HAL_TRIGGER_AAR_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_TRIGGER_AAR_PPI].TEP +#define HAL_TRIGGER_AAR_PPI_TASK \ + ((u32_t)&(NRF_AAR->TASKS_START)) + +/* Trigger Radio Rate override upon Rateboost event. */ +#if defined(CONFIG_SOC_NRF52840) +#define HAL_TRIGGER_RATEOVERRIDE_PPI 13 +#define HAL_TRIGGER_RATEOVERRIDE_PPI_ENABLE \ + ((PPI_CHENSET_CH13_Set << PPI_CHENSET_CH13_Pos) & PPI_CHENSET_CH13_Msk) +#define HAL_TRIGGER_RATEOVERRIDE_PPI_DISABLE \ + ((PPI_CHENCLR_CH13_Clear << PPI_CHENCLR_CH13_Pos) \ + & PPI_CHENCLR_CH13_Msk) +#define HAL_TRIGGER_RATEOVERRIDE_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_TRIGGER_RATEOVERRIDE_PPI].EEP +#define HAL_TRIGGER_RATEOVERRIDE_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_RATEBOOST)) +#define HAL_TRIGGER_RATEOVERRIDE_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_TRIGGER_RATEOVERRIDE_PPI].TEP +#define HAL_TRIGGER_RATEOVERRIDE_PPI_TASK \ + ((u32_t)&(NRF_CCM->TASKS_RATEOVERRIDE)) +#endif /* defined(CONFIG_SOC_NRF52840) */ + +#if defined(CONFIG_BT_CTLR_GPIO_PA_PIN) || defined(CONFIG_BT_CTLR_GPIO_LNA_PIN) +#define HAL_ENABLE_PALNA_PPI 14 +#define HAL_ENABLE_PALNA_PPI_ENABLE \ + ((PPI_CHENSET_CH14_Set << PPI_CHENSET_CH14_Pos) & PPI_CHENSET_CH14_Msk) +#define HAL_ENABLE_PALNA_PPI_DISABLE \ + ((PPI_CHENCLR_CH14_Clear << PPI_CHENCLR_CH14_Pos) \ + & PPI_CHENCLR_CH14_Msk) +#define HAL_ENABLE_PALNA_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_ENABLE_PALNA_PPI].EEP +#define HAL_ENABLE_PALNA_PPI_EVT \ + ((u32_t)&(EVENT_TIMER->EVENTS_COMPARE[2])) +#define HAL_ENABLE_PALNA_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_ENABLE_PALNA_PPI].TEP +#define HAL_ENABLE_PALNA_PPI_TASK \ + ((u32_t)&(NRF_GPIOTE->TASKS_OUT[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN])) + +#define HAL_DISABLE_PALNA_PPI 15 +#define HAL_DISABLE_PALNA_PPI_ENABLE \ + ((PPI_CHENSET_CH15_Set << PPI_CHENSET_CH15_Pos) & PPI_CHENSET_CH15_Msk) +#define HAL_DISABLE_PALNA_PPI_DISABLE \ + ((PPI_CHENCLR_CH15_Clear << PPI_CHENCLR_CH15_Pos) \ + & PPI_CHENCLR_CH15_Msk) +#define HAL_DISABLE_PALNA_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_DISABLE_PALNA_PPI].EEP +#define HAL_DISABLE_PALNA_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_DISABLED)) +#define HAL_DISABLE_PALNA_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_DISABLE_PALNA_PPI].TEP +#define HAL_DISABLE_PALNA_PPI_TASK \ + ((u32_t)&(NRF_GPIOTE->TASKS_OUT[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN])) +#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */ + +#if !defined(CONFIG_BT_CTLR_TIFS_HW) +/* PPI setup used for SW-based auto-switching during TIFS. */ + +/* Clear SW-switch timer on packet end: + * wire the RADIO EVENTS_END event to SW_SWITCH_TIMER TASKS_CLEAR task. + */ +#define HAL_SW_SWITCH_TIMER_CLEAR_PPI 7 +#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_ENABLE \ + ((PPI_CHENSET_CH7_Set << PPI_CHENSET_CH7_Pos) & PPI_CHENSET_CH7_Msk) +#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_DISABLE \ + ((PPI_CHENCLR_CH7_Clear << PPI_CHENCLR_CH7_Pos) & PPI_CHENCLR_CH7_Msk) +#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_SW_SWITCH_TIMER_CLEAR_PPI].EEP +#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_END)) +#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_SW_SWITCH_TIMER_CLEAR_PPI].TEP +#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_TASK \ + ((u32_t)&(SW_SWITCH_TIMER->TASKS_CLEAR)) + +/* The 2 adjacent PPI groups used for implementing SW_SWITCH_TIMER-based + * auto-switch for TIFS. 'index' must be 0 or 1. + */ +#define SW_SWITCH_TIMER_TASK_GROUP(index) \ + (SW_SWITCH_TIMER_TASK_GROUP_BASE + index) + +/* The 2 adjacent TIMER EVENTS_COMPARE event offsets used for implementing + * SW_SWITCH_TIMER-based auto-switch for TIFS. 'index' must be 0 or 1. + */ +#define SW_SWITCH_TIMER_EVTS_COMP(index) \ +(SW_SWITCH_TIMER_EVTS_COMP_BASE + index) + +/* Wire a SW SWITCH TIMER EVENTS_COMPARE[] event + * to a PPI GROUP TASK DISABLE task (PPI group with index ). + * 2 adjacent PPIs (8 & 9) and 2 adjacent PPI groups are used for this wiring; + * must be 0 or 1. must be a valid TIMER CC register offset. + */ +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 8 +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(index) \ + (HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE + index) +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE \ + ((PPI_CHG_CH8_Included << PPI_CHG_CH8_Pos) & PPI_CHG_CH8_Msk) +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_EXCLUDE \ + ((PPI_CHG_CH8_Excluded << PPI_CHG_CH8_Pos) & PPI_CHG_CH8_Msk) +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_1_INCLUDE \ + ((PPI_CHG_CH9_Included << PPI_CHG_CH9_Pos) & PPI_CHG_CH9_Msk) +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_1_EXCLUDE \ + ((PPI_CHG_CH9_Excluded << PPI_CHG_CH9_Pos) & PPI_CHG_CH9_Msk) +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(chan) \ + NRF_PPI->CH[chan].EEP +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc_offset) \ + ((u32_t)&(SW_SWITCH_TIMER->EVENTS_COMPARE[cc_offset])) +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(chan) \ + NRF_PPI->CH[chan].TEP +#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(index) \ + ((u32_t)&(NRF_PPI->TASKS_CHG[SW_SWITCH_TIMER_TASK_GROUP(index)].DIS)) + +/* Wire the RADIO EVENTS_END event to one of the PPI GROUP TASK ENABLE task. + * 2 adjacent PPI groups are used for this wiring. 'index' must be 0 or 1. + */ +#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI 10 +#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_ENABLE \ + ((PPI_CHENSET_CH10_Set << PPI_CHENSET_CH10_Pos) & PPI_CHENSET_CH10_Msk) +#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_DISABLE \ + ((PPI_CHENCLR_CH10_Clear << PPI_CHENCLR_CH10_Pos) \ + & PPI_CHENCLR_CH10_Msk) +#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI].EEP +#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_END)) +#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI].TEP +#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_TASK(index) \ + ((u32_t)&(NRF_PPI->TASKS_CHG[SW_SWITCH_TIMER_TASK_GROUP(index)].EN)) + +/*Enable Radio at specific time-stamp: + * wire the SW SWITCH TIMER EVENTS_COMPARE[] event + * to RADIO TASKS_TXEN/RXEN task. + * 2 adjacent PPIs (11 & 12) are used for this wiring; must be 0 or 1. + * must be a valid TIMER CC register offset. + */ +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 11 +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI(index) \ + (HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE + index) +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_0_INCLUDE \ + ((PPI_CHG_CH11_Included << PPI_CHG_CH11_Pos) & PPI_CHG_CH11_Msk) +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_0_EXCLUDE \ + ((PPI_CHG_CH11_Excluded << PPI_CHG_CH11_Pos) & PPI_CHG_CH11_Msk) +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_1_INCLUDE \ + ((PPI_CHG_CH12_Included << PPI_CHG_CH12_Pos) & PPI_CHG_CH12_Msk) +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_1_EXCLUDE \ + ((PPI_CHG_CH12_Excluded << PPI_CHG_CH12_Pos) & PPI_CHG_CH12_Msk) +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(chan) \ + NRF_PPI->CH[chan].EEP +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(cc_offset) \ + ((u32_t)&(SW_SWITCH_TIMER->EVENTS_COMPARE[cc_offset])) +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(chan) \ + NRF_PPI->CH[chan].TEP +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_TX \ + ((u32_t)&(NRF_RADIO->TASKS_TXEN)) +#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_RX \ + ((u32_t)&(NRF_RADIO->TASKS_RXEN)) + +#if defined(CONFIG_SOC_NRF52840) +/* The 2 adjacent TIMER EVENTS_COMPARE event offsets used for implementing + * SW_SWITCH_TIMER-based auto-switch for TIFS, when receiving in LE Coded PHY. + * 'index' must be 0 or 1. + */ +#define SW_SWITCH_TIMER_S2_EVTS_COMP(index) \ + (SW_SWITCH_TIMER_EVTS_COMP_S2_BASE + index) + +/* Wire the SW SWITCH TIMER EVENTS_COMPARE[] event + * to RADIO TASKS_TXEN/RXEN task. + * 2 adjacent PPIs (16 & 17) are used for this wiring; must be 0 or 1. + */ +#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE 16 +#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(index) \ + (HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE + index) +#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_0_INCLUDE \ + ((PPI_CHG_CH16_Included << PPI_CHG_CH16_Pos) & PPI_CHG_CH16_Msk) +#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_0_EXCLUDE \ + ((PPI_CHG_CH16_Excluded << PPI_CHG_CH16_Pos) & PPI_CHG_CH16_Msk) +#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_1_INCLUDE \ + ((PPI_CHG_CH17_Included << PPI_CHG_CH17_Pos) & PPI_CHG_CH17_Msk) +#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_1_EXCLUDE \ + ((PPI_CHG_CH17_Excluded << PPI_CHG_CH17_Pos) & PPI_CHG_CH17_Msk) + +/* Cancel the SW switch timer running considering S8 timing: + * wire the RADIO EVENTS_RATEBOOST event to SW_SWITCH_TIMER TASKS_CAPTURE task. + */ +#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI 18 +#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_ENABLE \ + ((PPI_CHENSET_CH18_Set << PPI_CHENSET_CH18_Pos) & PPI_CHENSET_CH18_Msk) +#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_DISABLE \ + ((PPI_CHENCLR_CH18_Clear << PPI_CHENCLR_CH18_Pos) \ + & PPI_CHENCLR_CH18_Msk) +#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT \ + NRF_PPI->CH[HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI].EEP +#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT \ + ((u32_t)&(NRF_RADIO->EVENTS_RATEBOOST)) +#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_TASK \ + NRF_PPI->CH[HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI].TEP +#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK(index) \ + ((u32_t)&(SW_SWITCH_TIMER->TASKS_CAPTURE[index])) + +#endif /* defined(CONFIG_SOC_NRF52840) */ + +#endif /* !defined(CONFIG_BT_CTLR_TIFS_HW) */ +#endif /* CONFIG_SOC_SERIES_NRF51X || CONFIG_SOC_SERIES_NRF52X */ diff --git a/subsys/bluetooth/controller/hal/radio.h b/subsys/bluetooth/controller/hal/radio.h index 096b27bb86b..b7f3f853046 100644 --- a/subsys/bluetooth/controller/hal/radio.h +++ b/subsys/bluetooth/controller/hal/radio.h @@ -25,7 +25,7 @@ void radio_pkt_rx_set(void *rx_packet); void radio_pkt_tx_set(void *tx_packet); u32_t radio_tx_ready_delay_get(u8_t phy, u8_t flags); u32_t radio_tx_chain_delay_get(u8_t phy, u8_t flags); -u32_t radio_rx_ready_delay_get(u8_t phy); +u32_t radio_rx_ready_delay_get(u8_t phy, u8_t flags); u32_t radio_rx_chain_delay_get(u8_t phy, u8_t flags); void radio_rx_enable(void); void radio_tx_enable(void); diff --git a/subsys/bluetooth/controller/ll_sw/ctrl.c b/subsys/bluetooth/controller/ll_sw/ctrl.c index 723978877c3..c616a00fe78 100644 --- a/subsys/bluetooth/controller/ll_sw/ctrl.c +++ b/subsys/bluetooth/controller/ll_sw/ctrl.c @@ -1104,7 +1104,7 @@ static inline u32_t isr_rx_adv(u8_t devmatch_ok, u8_t devmatch_id, pdu_adv->payload.connect_ind.lldata.win_size * 1250; conn->slave.window_size_prepare_us = 0; - rx_ready_delay = radio_rx_ready_delay_get(0); + rx_ready_delay = radio_rx_ready_delay_get(0, 0); /* calculate slave slot */ conn->hdr.ticks_slot = @@ -3741,7 +3741,7 @@ static inline u32_t isr_close_scan(void) radio_gpio_lna_setup(); radio_gpio_pa_lna_enable(start_us + - radio_rx_ready_delay_get(0) - + radio_rx_ready_delay_get(0, 0) - CONFIG_BT_CTLR_GPIO_LNA_OFFSET); #else /* !CONFIG_BT_CTLR_GPIO_LNA_PIN */ ARG_UNUSED(start_us); @@ -6205,7 +6205,7 @@ static void event_scan(u32_t ticks_at_expire, u32_t remainder, u16_t lazy, #if defined(CONFIG_BT_CTLR_GPIO_LNA_PIN) radio_gpio_lna_setup(); radio_gpio_pa_lna_enable(remainder_us + - radio_rx_ready_delay_get(0) - + radio_rx_ready_delay_get(0, 0) - CONFIG_BT_CTLR_GPIO_LNA_OFFSET); #else /* !CONFIG_BT_CTLR_GPIO_LNA_PIN */ ARG_UNUSED(remainder_us); @@ -7972,11 +7972,11 @@ static void event_slave(u32_t ticks_at_expire, u32_t remainder, u16_t lazy, conn->slave.window_size_event_us; #if defined(CONFIG_BT_CTLR_PHY) - hcto += radio_rx_ready_delay_get(conn->phy_rx); + hcto += radio_rx_ready_delay_get(conn->phy_rx, 1); hcto += addr_us_get(conn->phy_rx); hcto += radio_rx_chain_delay_get(conn->phy_rx, 1); #else /* !CONFIG_BT_CTLR_PHY */ - hcto += radio_rx_ready_delay_get(0); + hcto += radio_rx_ready_delay_get(0, 0); hcto += addr_us_get(0); hcto += radio_rx_chain_delay_get(0, 0); #endif /* !CONFIG_BT_CTLR_PHY */ @@ -7988,11 +7988,11 @@ static void event_slave(u32_t ticks_at_expire, u32_t remainder, u16_t lazy, #if defined(CONFIG_BT_CTLR_PHY) radio_gpio_pa_lna_enable(remainder_us + - radio_rx_ready_delay_get(conn->phy_rx) - + radio_rx_ready_delay_get(conn->phy_rx, 1) - CONFIG_BT_CTLR_GPIO_LNA_OFFSET); #else /* !CONFIG_BT_CTLR_PHY */ radio_gpio_pa_lna_enable(remainder_us + - radio_rx_ready_delay_get(0) - + radio_rx_ready_delay_get(0, 0) - CONFIG_BT_CTLR_GPIO_LNA_OFFSET); #endif /* !CONFIG_BT_CTLR_PHY */ #endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */ @@ -8202,11 +8202,11 @@ static void event_master(u32_t ticks_at_expire, u32_t remainder, u16_t lazy, #if defined(CONFIG_BT_CTLR_PHY) radio_gpio_pa_lna_enable(remainder_us + - radio_rx_ready_delay_get(conn->phy_rx) - + radio_rx_ready_delay_get(conn->phy_rx, 1) - CONFIG_BT_CTLR_GPIO_LNA_OFFSET); #else /* !CONFIG_BT_CTLR_PHY */ radio_gpio_pa_lna_enable(remainder_us + - radio_rx_ready_delay_get(0) - + radio_rx_ready_delay_get(0, 0) - CONFIG_BT_CTLR_GPIO_LNA_OFFSET); #endif /* !CONFIG_BT_CTLR_PHY */ #endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */