drivers: flash: stm32l4x: Support SOCs with < 1MB
Up to now, the only SOC that was supported in the STM32L496 series was STM32L496XG with flash of 1MB. With the recent support of STM32L496XE, this implementation is not correct. This patch adds support for the other SOCs that come with flashes of 512KB and 256KB. Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
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@ -1,6 +1,7 @@
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/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2017 BayLibre, SAS
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* Copyright (c) 2019 Centaur Analytics, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -114,8 +115,21 @@ static int erase_page(struct device *dev, unsigned int page)
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{
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struct stm32l4x_flash *regs = FLASH_STM32_REGS(dev);
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u32_t tmp;
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u16_t pages_per_bank;
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int rc;
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#if DT_FLASH_SIZE == 1024
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/* The SOC has 1MB of FLASH with DUALBANKing by design */
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pages_per_bank = 256U;
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#elif DT_FLASH_SIZE < 1024
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#ifdef FLASH_OPTR_DUALBANK
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/* DUALBANKing is used, so find the correct number of pages per bank */
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pages_per_bank = DT_FLASH_SIZE >> 2; /* Also there are two banks */
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#else
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pages_per_bank = DT_FLASH_SIZE >> 1; /* Each page is of 2KB size */
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#endif /* FLASH_OPTR_DUALBANK */
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#endif
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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@ -132,11 +146,11 @@ static int erase_page(struct device *dev, unsigned int page)
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#ifdef FLASH_CR_BKER
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regs->cr &= ~FLASH_CR_BKER_Msk;
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/* Select bank, only for DUALBANK devices */
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if (page >= 256U)
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if (page >= pages_per_bank)
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regs->cr |= FLASH_CR_BKER;
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#endif
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regs->cr &= ~FLASH_CR_PNB_Msk;
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regs->cr |= ((page % 256) << 3);
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regs->cr |= ((page % pages_per_bank) << 3);
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/* Set the STRT bit */
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regs->cr |= FLASH_CR_STRT;
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