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arch: arm64: arm_mpu: optimize ram region attribute

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Ram, ram_text and ram_ro regions will be accessed by all CPUs, so that
setting them to INNER_SHAREABLE is more reasonable.

'rbar' occupies 6 bits, correct it to 6.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This commit is contained in:
Huifeng Zhang 2023-08-30 14:38:43 +08:00 committed by Carles Cufí
parent 434ea2b2ff
commit 4eee1e8172
1 changed files with 19 additions and 19 deletions
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38
include/zephyr/arch/arm64/cortex_r/arm_mpu.h
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@ -140,12 +140,12 @@
.mair_idx = MPU_MAIR_INDEX_DEVICE, \
}
#define REGION_RAM_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
#define REGION_RAM_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RW_U_NA_Msk | INNER_SHAREABLE_Msk, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
#define REGION_RAM_NOCACHE_ATTR \
@ -156,20 +156,20 @@
.mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, \
}
#define REGION_RAM_TEXT_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
#define REGION_RAM_TEXT_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
#define REGION_RAM_RO_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RO_U_RO_Msk | NON_SHAREABLE_Msk, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
#define REGION_RAM_RO_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
@ -194,7 +194,7 @@
struct arm_mpu_region_attr {
/* Attributes belonging to PRBAR */
uint8_t rbar : 5;
uint8_t rbar : 6;
/* MAIR index for attribute indirection */
uint8_t mair_idx : 3;
};