bartoszek/zephyr
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

board: nsim: cleanup ARCv3 haps setup

Browse Source 
Cleanup ARCv3 haps setup with new cluster accessors

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This commit is contained in:
Evgeniy Paltsev 2023-12-22 16:29:40 +00:00 committed by Carles Cufí
parent d2b5ac20d1
commit 4e4a2e8d61
1 changed files with 8 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
boards/arc/nsim/haps_arcv3_init.c
View File

@ -1,48 +1,23 @@
/*
* Copyright (c) 2022 Synopsys
* Copyright (c) 2022-2023 Synopsys
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/arc/v2/aux_regs.h>
#include <zephyr/arch/arc/cluster.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#define ARC_CLN_MST_NOC_0_0_ADDR 292
#define ARC_CLN_MST_NOC_0_0_SIZE 293
#define ARC_CLN_MST_NOC_0_1_ADDR 2560
#define ARC_CLN_MST_NOC_0_1_SIZE 2561
#define ARC_CLN_MST_NOC_0_2_ADDR 2562
#define ARC_CLN_MST_NOC_0_2_SIZE 2563
#define ARC_CLN_MST_NOC_0_3_ADDR 2564
#define ARC_CLN_MST_NOC_0_3_SIZE 2565
#define ARC_CLN_MST_NOC_0_4_ADDR 2566
#define ARC_CLN_MST_NOC_0_4_SIZE 2567
#define ARC_CLN_PER0_BASE 2688
#define ARC_CLN_PER0_SIZE 2689
#define AUX_CLN_ADDR 0x640
#define AUX_CLN_DATA 0x641
#define DT_SRAM_NODE_ADDR (DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) / (1024 * 1024))
#define DT_SRAM_NODE_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) / (1024 * 1024))
static int haps_arcv3_init(void)
{
arc_cln_write_reg_nolock(ARC_CLN_PER0_BASE, 0xF00);
arc_cln_write_reg_nolock(ARC_CLN_PER0_SIZE, 1);
z_arc_v2_aux_reg_write(AUX_CLN_ADDR, ARC_CLN_PER0_BASE);
z_arc_v2_aux_reg_write(AUX_CLN_DATA, 0xF00);
z_arc_v2_aux_reg_write(AUX_CLN_ADDR, ARC_CLN_PER0_SIZE);
z_arc_v2_aux_reg_write(AUX_CLN_DATA, 1);
z_arc_v2_aux_reg_write(AUX_CLN_ADDR, ARC_CLN_MST_NOC_0_0_ADDR);
z_arc_v2_aux_reg_write(AUX_CLN_DATA, (DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) / (1024 * 1024)));
z_arc_v2_aux_reg_write(AUX_CLN_ADDR, ARC_CLN_MST_NOC_0_0_SIZE);
z_arc_v2_aux_reg_write(AUX_CLN_DATA, (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) / (1024 * 1024)));
arc_cln_write_reg_nolock(ARC_CLN_MST_NOC_0_0_ADDR, DT_SRAM_NODE_ADDR);
arc_cln_write_reg_nolock(ARC_CLN_MST_NOC_0_0_SIZE, DT_SRAM_NODE_SIZE);
return 0;
}