From 4c93fcd35b27326a557e8077902eb94ce9afb237 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Wed, 9 Jul 2025 23:31:55 +0800 Subject: [PATCH] tests: arm: sw_vector_table: enhance test configs for frdm_mcxa166 irq 0 in frdm_mcxa166/276 are reserved can not used for testing. add a config to shift test irq, also add support for rt700 also fix irq1 issue on mimxrt1180 as it is a debug trace interrupt fixes: #92877, #92521 Signed-off-by: Hake Huang --- tests/arch/arm/arm_irq_vector_table/Kconfig | 4 ++++ .../boards/frdm_mcxa166.conf | 1 + .../boards/frdm_mcxa276.conf | 1 + .../mimxrt1180_evk_mimxrt1189_cm33.conf | 1 + .../src/arm_irq_vector_table.c | 24 ++++++++++++++++--- 5 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa166.conf create mode 100644 tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa276.conf create mode 100644 tests/arch/arm/arm_irq_vector_table/boards/mimxrt1180_evk_mimxrt1189_cm33.conf diff --git a/tests/arch/arm/arm_irq_vector_table/Kconfig b/tests/arch/arm/arm_irq_vector_table/Kconfig index 9d231dd4544..d7c4fd36716 100644 --- a/tests/arch/arm/arm_irq_vector_table/Kconfig +++ b/tests/arch/arm/arm_irq_vector_table/Kconfig @@ -4,4 +4,8 @@ config NUM_IRQS int "Number of IRQs for this test, made overridable in the .conf file" default 3 +config ISR_OFFSET + int "isr offset from vector table" + default 0 + source "Kconfig.zephyr" diff --git a/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa166.conf b/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa166.conf new file mode 100644 index 00000000000..f8331d65801 --- /dev/null +++ b/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa166.conf @@ -0,0 +1 @@ +CONFIG_ISR_OFFSET=39 diff --git a/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa276.conf b/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa276.conf new file mode 100644 index 00000000000..f8331d65801 --- /dev/null +++ b/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa276.conf @@ -0,0 +1 @@ +CONFIG_ISR_OFFSET=39 diff --git a/tests/arch/arm/arm_irq_vector_table/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/tests/arch/arm/arm_irq_vector_table/boards/mimxrt1180_evk_mimxrt1189_cm33.conf new file mode 100644 index 00000000000..47c18f8e610 --- /dev/null +++ b/tests/arch/arm/arm_irq_vector_table/boards/mimxrt1180_evk_mimxrt1189_cm33.conf @@ -0,0 +1 @@ +CONFIG_ISR_OFFSET=4 diff --git a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c index 1974f3af786..07ff53d0934 100644 --- a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c +++ b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include #include @@ -13,7 +14,7 @@ * Offset (starting from the beginning of the vector table) * of the location where the ISRs will be manually installed. */ -#define _ISR_OFFSET 0 +#define _ISR_OFFSET CONFIG_ISR_OFFSET #if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) #undef _ISR_OFFSET @@ -108,7 +109,8 @@ ZTEST(vector_table, test_arm_irq_vector_table) k_sem_take(&sem[2], K_NO_WAIT))); for (int ii = 0; ii < 3; ii++) { -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || defined(CONFIG_SOC_TI_LM3S6965_QEMU) +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || defined(CONFIG_SOC_TI_LM3S6965_QEMU) || \ + defined(CONFIG_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* the QEMU does not simulate the * STIR register: this is a workaround */ @@ -242,7 +244,23 @@ const vth __irq_vector_table _irq_vector_table[] = { #error "GPT timer enabled, but no known SOC selected. ISR table needs rework" #endif #else -const vth __irq_vector_table _irq_vector_table[] = {isr0, isr1, isr2}; + +#if defined(CONFIG_MCUX_OS_TIMER) +extern void mcux_lpc_ostick_isr(void); +#define TIMER_IRQ_NUM DT_IRQN(DT_INST(0, nxp_os_timer)) +#define TIMER_IRQ_HANDLER mcux_lpc_ostick_isr +#define IRQ_VECTOR_TABLE_SIZE _ISR_OFFSET > TIMER_IRQ_NUM ? (_ISR_OFFSET + 3) : (TIMER_IRQ_NUM + 1) +#else +#define IRQ_VECTOR_TABLE_SIZE (_ISR_OFFSET + 3) +#endif /* CONFIG_MCUX_OS_TIMER */ +const vth __irq_vector_table _irq_vector_table[IRQ_VECTOR_TABLE_SIZE] = { + [_ISR_OFFSET] = isr0, + [_ISR_OFFSET + 1] = isr1, + [_ISR_OFFSET + 2] = isr2, +#ifndef CONFIG_CORTEX_M_SYSTICK + [TIMER_IRQ_NUM] = TIMER_IRQ_HANDLER, +#endif +}; #endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ /**