From 4958a5fb6cb374c9c9db2b8313c2737d2911e686 Mon Sep 17 00:00:00 2001 From: Amneesh Singh Date: Thu, 6 Mar 2025 14:01:53 +0530 Subject: [PATCH] soc: ti_k3: specify soc-specific ctrl partitions The first two partitions in padconfig mmr regions need to be unlocked for the pinctrl driver to be able to write. However, the base addresses for the the registers can be different across SoCs and domains. Besides, currently this is only done for M4 and that too not in the local (M4's) view. This patch introduces a file specifying all ctrl partition base addresses using ifdef directives for different SoCs and variants, and unlocking them before the kernel and drivers initialize. Signed-off-by: Amneesh Singh --- soc/ti/k3/am6x/CMakeLists.txt | 1 + soc/ti/k3/am6x/Kconfig | 1 + soc/ti/k3/am6x/common/ctrl_partitions.c | 48 +++++++++++++++++++++++++ soc/ti/k3/am6x/common/ctrl_partitions.h | 12 +++++++ soc/ti/k3/am6x/m4/soc.c | 31 +++------------- soc/ti/k3/am6x/r5/soc.c | 6 ++++ 6 files changed, 73 insertions(+), 26 deletions(-) create mode 100644 soc/ti/k3/am6x/common/ctrl_partitions.c create mode 100644 soc/ti/k3/am6x/common/ctrl_partitions.h diff --git a/soc/ti/k3/am6x/CMakeLists.txt b/soc/ti/k3/am6x/CMakeLists.txt index d5e88b78e25..79e4cd12596 100644 --- a/soc/ti/k3/am6x/CMakeLists.txt +++ b/soc/ti/k3/am6x/CMakeLists.txt @@ -2,6 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) +zephyr_sources(common/ctrl_partitions.c) if(CONFIG_SOC_AM6234_A53) zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c) diff --git a/soc/ti/k3/am6x/Kconfig b/soc/ti/k3/am6x/Kconfig index 504e044184a..e690eacb246 100644 --- a/soc/ti/k3/am6x/Kconfig +++ b/soc/ti/k3/am6x/Kconfig @@ -30,6 +30,7 @@ config SOC_SERIES_AM6X_R5 select TI_DM_TIMER select OPENAMP_RSC_TABLE select UART_NS16550_ACCESS_WORD_ONLY if UART_NS16550 + select SOC_EARLY_INIT_HOOK config SOC_PART_NUMBER default "AM6234" if SOC_AM6234_A53 diff --git a/soc/ti/k3/am6x/common/ctrl_partitions.c b/soc/ti/k3/am6x/common/ctrl_partitions.c new file mode 100644 index 00000000000..48d5c3cdc86 --- /dev/null +++ b/soc/ti/k3/am6x/common/ctrl_partitions.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#define KICK0_OFFSET (0x1008) +#define KICK1_OFFSET (0x100C) +#define KICK0_UNLOCK_VAL (0x68EF3490U) +#define KICK1_UNLOCK_VAL (0xD172BC5AU) +#define KICK_LOCK_VAL (0x0U) + +#define CTRL_PARTITION_SIZE (0x4000) +#define CTRL_PARTITION(base, part) ((base) + (part) * CTRL_PARTITION_SIZE) + +#if defined CONFIG_SOC_AM6442_M4 +#define MCU_PADCFG_BASE (0x4080000) +#elif defined CONFIG_SOC_AM6234_M4 +#define WKUP_PADCFG_BASE (0x4080000) +#endif + +static const uintptr_t ctrl_partitions[] = { +#if defined CONFIG_SOC_AM6442_M4 + CTRL_PARTITION(MCU_PADCFG_BASE, 0), + CTRL_PARTITION(MCU_PADCFG_BASE, 1), +#elif defined CONFIG_SOC_AM6234_M4 + CTRL_PARTITION(WKUP_PADCFG_BASE, 0), + CTRL_PARTITION(WKUP_PADCFG_BASE, 1), +#endif +}; + +void k3_unlock_all_ctrl_partitions(void) +{ + ARRAY_FOR_EACH(ctrl_partitions, i) { + mm_reg_t base_addr = ctrl_partitions[i]; + +#ifdef DEVICE_MMIO_IS_IN_RAM + device_map(&base_addr, base_addr, sizeof(base_addr), K_MEM_CACHE_NONE); +#endif + + sys_write32(KICK0_UNLOCK_VAL, base_addr + KICK0_OFFSET); + sys_write32(KICK1_UNLOCK_VAL, base_addr + KICK1_OFFSET); + } +} diff --git a/soc/ti/k3/am6x/common/ctrl_partitions.h b/soc/ti/k3/am6x/common/ctrl_partitions.h new file mode 100644 index 00000000000..a2b1b0d8839 --- /dev/null +++ b/soc/ti/k3/am6x/common/ctrl_partitions.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __K3_CTRL_PARTITIONS_H_ +#define __K3_CTRL_PARTITIONS_H_ + +void k3_unlock_all_ctrl_partitions(void); + +#endif /* __K3_CTRL_PARTITIONS_H */ diff --git a/soc/ti/k3/am6x/m4/soc.c b/soc/ti/k3/am6x/m4/soc.c index c1cf4d9fbcf..40dc0a7c92a 100644 --- a/soc/ti/k3/am6x/m4/soc.c +++ b/soc/ti/k3/am6x/m4/soc.c @@ -4,18 +4,14 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include #include #include #include -#define ADDR_TRANSLATE_RAT_BASE_ADDR (0x44200000u) -#define PINCTRL_BASE_ADDR (0x04080000u) -#define KICK0_UNLOCK_VAL (0x68EF3490U) -#define KICK1_UNLOCK_VAL (0xD172BC5AU) -#define CSL_MCU_PADCONFIG_LOCK0_KICK0_OFFSET (0x1008) -#define CSL_MCU_PADCONFIG_LOCK1_KICK0_OFFSET (0x5008) +#define ADDR_TRANSLATE_RAT_BASE_ADDR (0x44200000u) static struct address_trans_region_config am6x_region_config[] = { { @@ -38,27 +34,10 @@ static struct address_trans_region_config am6x_region_config[] = { */ }; -static void am6x_mmr_unlock(void) -{ - uint32_t baseAddr = PINCTRL_BASE_ADDR; - uintptr_t kickAddr; - - /* Lock 0 */ - kickAddr = baseAddr + CSL_MCU_PADCONFIG_LOCK0_KICK0_OFFSET; - sys_write32(KICK0_UNLOCK_VAL, kickAddr); /* KICK 0 */ - kickAddr = kickAddr + sizeof(uint32_t *); - sys_write32(KICK1_UNLOCK_VAL, kickAddr); /* KICK 1 */ - - /* Lock 1 */ - kickAddr = baseAddr + CSL_MCU_PADCONFIG_LOCK1_KICK0_OFFSET; - sys_write32(KICK0_UNLOCK_VAL, kickAddr); /* KICK 0 */ - kickAddr = kickAddr + sizeof(uint32_t *); - sys_write32(KICK1_UNLOCK_VAL, kickAddr); /* KICK 1 */ -} - void soc_early_init_hook(void) { sys_mm_drv_ti_rat_init(am6x_region_config, ADDR_TRANSLATE_RAT_BASE_ADDR, - ARRAY_SIZE(am6x_region_config)); - am6x_mmr_unlock(); + ARRAY_SIZE(am6x_region_config)); + + k3_unlock_all_ctrl_partitions(); } diff --git a/soc/ti/k3/am6x/r5/soc.c b/soc/ti/k3/am6x/r5/soc.c index 8190f43353f..3142fdcd96f 100644 --- a/soc/ti/k3/am6x/r5/soc.c +++ b/soc/ti/k3/am6x/r5/soc.c @@ -8,6 +8,7 @@ #include #include "soc.h" +#include unsigned int z_soc_irq_get_active(void) { @@ -47,3 +48,8 @@ int z_soc_irq_is_enabled(unsigned int irq) /* Check if interrupt is enabled */ return z_vim_irq_is_enabled(irq); } + +void soc_early_init_hook(void) +{ + k3_unlock_all_ctrl_partitions(); +}