From 47564a09714fc5a27dcb390205d89046970621d6 Mon Sep 17 00:00:00 2001 From: Ioannis Glaropoulos Date: Mon, 12 Feb 2018 08:22:16 +0100 Subject: [PATCH] arch: arm: feature consistency checks for Cortex M regs This commit implements consistency checks for the core registers in ARMv6-M, ARMv7-M, and ARMv8-M architectures, ensuring that the user cannot accidentally select registers that are not implemented by the selected Cortex-M processor. Signed-off-by: Ioannis Glaropoulos --- arch/arm/core/cortex_m/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index 66df3c55e6e..ebc443e2ce0 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -106,16 +106,31 @@ config ISA_THUMB2 config CPU_CORTEX_M_HAS_BASEPRI bool # Omit prompt to signify "hidden" option + depends on ARMV7_M_ARMV8_M_MAINLINE default n help This option signifies the CPU has the BASEPRI register. + The BASEPRI register defines the minimum priority for + exception processing. When BASEPRI is set to a nonzero + value, it prevents the activation of all exceptions with + the same or lower priority level as the BASEPRI value. + Always present in CPUs that implement the ARMv7-M or + ARM8-M Mainline architectures. + config CPU_CORTEX_M_HAS_VTOR bool # Omit prompt to signify "hidden" option + depends on !CPU_CORTEX_M0 default n help This option signifies the CPU has the VTOR register. + The VTOR indicates the offset of the vector table base + address from memory address 0x00000000. Always present + in CPUs implementing the ARMv7-M or ARMv8-M architetures. + Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline + architetures (except for Cortex-M0, where it is never + implemented). config CPU_CORTEX_M_HAS_SPLIM bool