From 444d214211c64eeea2516488eb01810693d4e220 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 23 Feb 2022 13:57:38 +0100 Subject: [PATCH] test: mpu: Add arm_mpu_regions test A a test for the new DT-configured memory regions. Signed-off-by: Carlo Caione --- tests/misc/arm_mpu_regions/CMakeLists.txt | 8 +++ .../arm_mpu_regions/boards/mps2_an385.overlay | 41 +++++++++++++ tests/misc/arm_mpu_regions/prj.conf | 1 + tests/misc/arm_mpu_regions/src/main.c | 60 +++++++++++++++++++ tests/misc/arm_mpu_regions/testcase.yaml | 4 ++ 5 files changed, 114 insertions(+) create mode 100644 tests/misc/arm_mpu_regions/CMakeLists.txt create mode 100644 tests/misc/arm_mpu_regions/boards/mps2_an385.overlay create mode 100644 tests/misc/arm_mpu_regions/prj.conf create mode 100644 tests/misc/arm_mpu_regions/src/main.c create mode 100644 tests/misc/arm_mpu_regions/testcase.yaml diff --git a/tests/misc/arm_mpu_regions/CMakeLists.txt b/tests/misc/arm_mpu_regions/CMakeLists.txt new file mode 100644 index 00000000000..b847ef0b65d --- /dev/null +++ b/tests/misc/arm_mpu_regions/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(arm_mpu_regions) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/misc/arm_mpu_regions/boards/mps2_an385.overlay b/tests/misc/arm_mpu_regions/boards/mps2_an385.overlay new file mode 100644 index 00000000000..e882e13075d --- /dev/null +++ b/tests/misc/arm_mpu_regions/boards/mps2_an385.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 Carlo Caione + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /delete-node/ memory@20000000; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x200000>; + }; + + sram_cache: memory@20200000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20200000 0x100000>; + zephyr,memory-region = "SRAM_CACHE"; + zephyr,memory-region-mpu = "RAM"; + }; + + sram_no_cache: memory@20300000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20300000 0x100000>; + zephyr,memory-region = "SRAM_NO_CACHE"; + zephyr,memory-region-mpu = "RAM_NOCACHE"; + }; + + sram_dtcm_fake: memory@abcdabcd { + compatible = "zephyr,memory-region", "arm,dtcm"; + reg = <0xabcdabcd 0x100000>; + zephyr,memory-region = "SRAM_DTCM_FAKE"; + zephyr,memory-region-mpu = "RAM"; + }; + + sram_no_mpu: memory@deaddead { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0xdeaddead 0x100000>; + zephyr,memory-region = "SRAM_NO_MPU"; + }; +}; diff --git a/tests/misc/arm_mpu_regions/prj.conf b/tests/misc/arm_mpu_regions/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/tests/misc/arm_mpu_regions/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/tests/misc/arm_mpu_regions/src/main.c b/tests/misc/arm_mpu_regions/src/main.c new file mode 100644 index 00000000000..322c7a86bfb --- /dev/null +++ b/tests/misc/arm_mpu_regions/src/main.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2021 Carlo Caione + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +extern const struct arm_mpu_config mpu_config; + +static arm_mpu_region_attr_t cacheable = REGION_RAM_ATTR(REGION_1M); +static arm_mpu_region_attr_t noncacheable = REGION_RAM_NOCACHE_ATTR(REGION_1M); + +static void test_regions(void) +{ + int cnt = 0; + + for (size_t i = 0; i < mpu_config.num_regions; i++) { + const struct arm_mpu_region *r = &mpu_config.mpu_regions[i]; + + if (!strcmp(r->name, "SRAM_CACHE")) { + zassert_equal(r->base, 0x20200000, "Wrong base"); + zassert_equal(r->attr.rasr, cacheable.rasr, + "Wrong attr for SRAM_CACHE"); + cnt++; + } else if (!strcmp(r->name, "SRAM_NO_CACHE")) { + zassert_equal(r->base, 0x20300000, "Wrong base"); + zassert_equal(r->attr.rasr, noncacheable.rasr, + "Wrong attr for SRAM_NO_CACHE"); + cnt++; + } else if (!strcmp(r->name, "SRAM_DTCM_FAKE")) { + zassert_equal(r->base, 0xabcdabcd, "Wrong base"); + zassert_equal(r->attr.rasr, cacheable.rasr, + "Wrong attr for SRAM_DTCM_FAKE"); + cnt++; + } + } + + if (cnt != 3) { + /* + * SRAM0 and SRAM_NO_MPU should not create any MPU region. + * Check that. + */ + ztest_test_fail(); + } +} + +void test_main(void) +{ + ztest_test_suite(test_c_arm_mpu_regions, + ztest_unit_test(test_regions) + ); + + ztest_run_test_suite(test_c_arm_mpu_regions); +} diff --git a/tests/misc/arm_mpu_regions/testcase.yaml b/tests/misc/arm_mpu_regions/testcase.yaml new file mode 100644 index 00000000000..500f4268686 --- /dev/null +++ b/tests/misc/arm_mpu_regions/testcase.yaml @@ -0,0 +1,4 @@ +tests: + misc.arm_mpu_regions: + platform_allow: mps2_an385 + tags: sample board sram mpu