From 43079c80869df00a26cacc9750407cadb0b733ed Mon Sep 17 00:00:00 2001 From: Terry Geng Date: Mon, 27 Jan 2025 10:00:24 -0500 Subject: [PATCH] drivers: adc: ads114s0x: Rename variables, preparing for adding new devices Renamed ads114s0x/8 to ads1x4s0x. Signed-off-by: Terry Geng --- drivers/adc/CMakeLists.txt | 2 +- drivers/adc/Kconfig.ads114s0x | 30 +- drivers/adc/adc_ads114s0x.c | 1080 ++++++++--------- drivers/gpio/CMakeLists.txt | 2 +- drivers/gpio/Kconfig.ads114s0x | 22 +- drivers/gpio/gpio_ads114s0x.c | 88 +- dts/bindings/gpio/ti,ads114s0x-gpio.yaml | 2 +- include/zephyr/drivers/adc/ads114s0x.h | 22 +- .../zephyr/dt-bindings/adc/ads114s0x_adc.h | 34 +- .../gpio/adc_ads1145s0x_gpio.overlay | 2 +- tests/drivers/build_all/gpio/testcase.yaml | 4 +- 11 files changed, 644 insertions(+), 644 deletions(-) diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt index e0d77e5f48c..bb0227f0139 100644 --- a/drivers/adc/CMakeLists.txt +++ b/drivers/adc/CMakeLists.txt @@ -34,7 +34,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_GD32 adc_gd32.c) zephyr_library_sources_ifdef(CONFIG_ADC_ADS1112 adc_ads1112.c) zephyr_library_sources_ifdef(CONFIG_ADC_ADS1119 adc_ads1119.c) zephyr_library_sources_ifdef(CONFIG_ADC_ADS7052 adc_ads7052.c) -zephyr_library_sources_ifdef(CONFIG_ADC_ADS114S0X adc_ads114s0x.c) +zephyr_library_sources_ifdef(CONFIG_ADC_ADS1X4S0X adc_ads114s0x.c) zephyr_library_sources_ifdef(CONFIG_ADC_ADS131M02 adc_ads131m02.c) zephyr_library_sources_ifdef(CONFIG_ADC_RPI_PICO adc_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_ADC_XMC4XXX adc_xmc4xxx.c) diff --git a/drivers/adc/Kconfig.ads114s0x b/drivers/adc/Kconfig.ads114s0x index 45191bb92ea..6ea48b13086 100644 --- a/drivers/adc/Kconfig.ads114s0x +++ b/drivers/adc/Kconfig.ads114s0x @@ -2,43 +2,43 @@ # # SPDX-License-Identifier: Apache-2.0 -menuconfig ADC_ADS114S0X - bool "Texas instruments ADS114S0x" +menuconfig ADC_ADS1X4S0X + bool "Texas instruments ADS1X4S0X" default y - depends on DT_HAS_TI_ADS114S08_ENABLED + depends on DT_HAS_TI_ADS1X4S08_ENABLED select SPI select ADC_CONFIGURABLE_INPUTS select ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN select ADC_CONFIGURABLE_VBIAS_PIN help - Enable the driver implementation for the ADS114S0X family + Enable the driver implementation for the ADS1X4S0X family -config ADC_ADS114S0X_ASYNC_THREAD_INIT_PRIO - int "ADC ADS114S0x async thread priority" +config ADC_ADS1X4S0X_ASYNC_THREAD_INIT_PRIO + int "ADC ADS1X4S0X async thread priority" default 0 - depends on ADC_ADS114S0X + depends on ADC_ADS1X4S0X -config ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE +config ADC_ADS1X4S0X_ACQUISITION_THREAD_STACK_SIZE int "Stack size for the ADC data acquisition thread" default 400 - depends on ADC_ADS114S0X + depends on ADC_ADS1X4S0X help Size of the stack used for the internal data acquisition thread. -config ADC_ADS114S0X_GPIO +config ADC_ADS1X4S0X_GPIO bool "GPIO support" default n - depends on GPIO && ADC_ADS114S0X + depends on GPIO && ADC_ADS1X4S0X help - Enable GPIO child device support in the ADS114S0x ADC driver. + Enable GPIO child device support in the ADS1X4S0X ADC driver. - The GPIO functionality is handled by the ADS114S0x GPIO + The GPIO functionality is handled by the ADS1X4S0X GPIO driver. -config ADC_ADS114S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS +config ADC_ADS1X4S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS int "Timeout for wait for completion of a read in ms" default 1000 - depends on ADC_ADS114S0X + depends on ADC_ADS1X4S0X help This is the wait time in ms until a read is completed. diff --git a/drivers/adc/adc_ads114s0x.c b/drivers/adc/adc_ads114s0x.c index 36e3eaefac4..61358cab1ab 100644 --- a/drivers/adc/adc_ads114s0x.c +++ b/drivers/adc/adc_ads114s0x.c @@ -18,347 +18,347 @@ #define ADC_CONTEXT_USES_KERNEL_TIMER 1 #define ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT \ - K_MSEC(CONFIG_ADC_ADS114S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS) + K_MSEC(CONFIG_ADC_ADS1X4S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS) #include "adc_context.h" -LOG_MODULE_REGISTER(ads114s0x, CONFIG_ADC_LOG_LEVEL); +LOG_MODULE_REGISTER(ads1x4s0x, CONFIG_ADC_LOG_LEVEL); -#define ADS114S0X_CLK_FREQ_IN_KHZ 4096 -#define ADS114S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES 4 -#define ADS114S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES 4 -#define ADS114S0X_SETUP_TIME_IN_CLOCK_CYCLES 32 -#define ADS114S0X_INPUT_SELECTION_AINCOM 12 -#define ADS114S0X_RESOLUTION 16 -#define ADS114S0X_REF_INTERNAL 2500 -#define ADS114S0X_GPIO_MAX 3 -#define ADS114S0X_POWER_ON_RESET_TIME_IN_US 2200 -#define ADS114S0X_VBIAS_PIN_MAX 7 -#define ADS114S0X_VBIAS_PIN_MIN 0 +#define ADS1X4S0X_CLK_FREQ_IN_KHZ 4096 +#define ADS1X4S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES 4 +#define ADS1X4S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES 4 +#define ADS1X4S0X_SETUP_TIME_IN_CLOCK_CYCLES 32 +#define ADS1X4S0X_INPUT_SELECTION_AINCOM 12 +#define ADS1X4S0X_RESOLUTION 16 +#define ADS1X4S0X_REF_INTERNAL 2500 +#define ADS1X4S0X_GPIO_MAX 3 +#define ADS1X4S0X_POWER_ON_RESET_TIME_IN_US 2200 +#define ADS1X4S0X_VBIAS_PIN_MAX 7 +#define ADS1X4S0X_VBIAS_PIN_MIN 0 /* Not mentioned in the datasheet, but instead determined experimentally. */ -#define ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US 1000 -#define ADS114S0X_RESET_DELAY_TIME_IN_US \ - (4096 * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ + ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US) +#define ADS1X4S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US 1000 +#define ADS1X4S0X_RESET_DELAY_TIME_IN_US \ + (4096 * 1000 / ADS1X4S0X_CLK_FREQ_IN_KHZ + ADS1X4S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US) -#define ADS114S0X_RESET_LOW_TIME_IN_US \ - (ADS114S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ) -#define ADS114S0X_START_SYNC_PULSE_DURATION_IN_US \ - (ADS114S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ) -#define ADS114S0X_SETUP_TIME_IN_US \ - (ADS114S0X_SETUP_TIME_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ) +#define ADS1X4S0X_RESET_LOW_TIME_IN_US \ + (ADS1X4S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES * 1000 / ADS1X4S0X_CLK_FREQ_IN_KHZ) +#define ADS1X4S0X_START_SYNC_PULSE_DURATION_IN_US \ + (ADS1X4S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES * 1000 / ADS1X4S0X_CLK_FREQ_IN_KHZ) +#define ADS1X4S0X_SETUP_TIME_IN_US \ + (ADS1X4S0X_SETUP_TIME_IN_CLOCK_CYCLES * 1000 / ADS1X4S0X_CLK_FREQ_IN_KHZ) -enum ads114s0x_command { - ADS114S0X_COMMAND_NOP = 0x00, - ADS114S0X_COMMAND_WAKEUP = 0x02, - ADS114S0X_COMMAND_POWERDOWN = 0x04, - ADS114S0X_COMMAND_RESET = 0x06, - ADS114S0X_COMMAND_START = 0x08, - ADS114S0X_COMMAND_STOP = 0x0A, - ADS114S0X_COMMAND_SYOCAL = 0x16, - ADS114S0X_COMMAND_SYGCAL = 0x17, - ADS114S0X_COMMAND_SFOCAL = 0x19, - ADS114S0X_COMMAND_RDATA = 0x12, - ADS114S0X_COMMAND_RREG = 0x20, - ADS114S0X_COMMAND_WREG = 0x40, +enum ads1x4s0x_command { + ADS1X4S0X_COMMAND_NOP = 0x00, + ADS1X4S0X_COMMAND_WAKEUP = 0x02, + ADS1X4S0X_COMMAND_POWERDOWN = 0x04, + ADS1X4S0X_COMMAND_RESET = 0x06, + ADS1X4S0X_COMMAND_START = 0x08, + ADS1X4S0X_COMMAND_STOP = 0x0A, + ADS1X4S0X_COMMAND_SYOCAL = 0x16, + ADS1X4S0X_COMMAND_SYGCAL = 0x17, + ADS1X4S0X_COMMAND_SFOCAL = 0x19, + ADS1X4S0X_COMMAND_RDATA = 0x12, + ADS1X4S0X_COMMAND_RREG = 0x20, + ADS1X4S0X_COMMAND_WREG = 0x40, }; -enum ads114s0x_register { - ADS114S0X_REGISTER_ID = 0x00, - ADS114S0X_REGISTER_STATUS = 0x01, - ADS114S0X_REGISTER_INPMUX = 0x02, - ADS114S0X_REGISTER_PGA = 0x03, - ADS114S0X_REGISTER_DATARATE = 0x04, - ADS114S0X_REGISTER_REF = 0x05, - ADS114S0X_REGISTER_IDACMAG = 0x06, - ADS114S0X_REGISTER_IDACMUX = 0x07, - ADS114S0X_REGISTER_VBIAS = 0x08, - ADS114S0X_REGISTER_SYS = 0x09, - ADS114S0X_REGISTER_OFCAL0 = 0x0B, - ADS114S0X_REGISTER_OFCAL1 = 0x0C, - ADS114S0X_REGISTER_FSCAL0 = 0x0E, - ADS114S0X_REGISTER_FSCAL1 = 0x0F, - ADS114S0X_REGISTER_GPIODAT = 0x10, - ADS114S0X_REGISTER_GPIOCON = 0x11, +enum ads1x4s0x_register { + ADS1X4S0X_REGISTER_ID = 0x00, + ADS1X4S0X_REGISTER_STATUS = 0x01, + ADS1X4S0X_REGISTER_INPMUX = 0x02, + ADS1X4S0X_REGISTER_PGA = 0x03, + ADS1X4S0X_REGISTER_DATARATE = 0x04, + ADS1X4S0X_REGISTER_REF = 0x05, + ADS1X4S0X_REGISTER_IDACMAG = 0x06, + ADS1X4S0X_REGISTER_IDACMUX = 0x07, + ADS1X4S0X_REGISTER_VBIAS = 0x08, + ADS1X4S0X_REGISTER_SYS = 0x09, + ADS1X4S0X_REGISTER_OFCAL0 = 0x0B, + ADS1X4S0X_REGISTER_OFCAL1 = 0x0C, + ADS1X4S0X_REGISTER_FSCAL0 = 0x0E, + ADS1X4S0X_REGISTER_FSCAL1 = 0x0F, + ADS1X4S0X_REGISTER_GPIODAT = 0x10, + ADS1X4S0X_REGISTER_GPIOCON = 0x11, }; -#define ADS114S0X_REGISTER_GET_VALUE(value, pos, length) \ +#define ADS1X4S0X_REGISTER_GET_VALUE(value, pos, length) \ FIELD_GET(GENMASK(pos + length - 1, pos), value) -#define ADS114S0X_REGISTER_SET_VALUE(target, value, pos, length) \ +#define ADS1X4S0X_REGISTER_SET_VALUE(target, value, pos, length) \ target &= ~GENMASK(pos + length - 1, pos); \ target |= FIELD_PREP(GENMASK(pos + length - 1, pos), value) -#define ADS114S0X_REGISTER_ID_DEV_ID_LENGTH 3 -#define ADS114S0X_REGISTER_ID_DEV_ID_POS 0 -#define ADS114S0X_REGISTER_ID_DEV_ID_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_ID_DEV_ID_POS, \ - ADS114S0X_REGISTER_ID_DEV_ID_LENGTH) -#define ADS114S0X_REGISTER_ID_DEV_ID_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_ID_DEV_ID_POS, \ - ADS114S0X_REGISTER_ID_DEV_ID_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH 1 -#define ADS114S0X_REGISTER_STATUS_FL_POR_POS 7 -#define ADS114S0X_REGISTER_STATUS_FL_POR_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_POR_POS, \ - ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_POR_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_POR_POS, \ - ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH) -#define ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH 1 -#define ADS114S0X_REGISTER_STATUS_NOT_RDY_POS 6 -#define ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_NOT_RDY_POS, \ - ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH) -#define ADS114S0X_REGISTER_STATUS_NOT_RDY_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_NOT_RDY_POS, \ - ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH 1 -#define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS 5 -#define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS, \ - ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS, \ - ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH 1 -#define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS 4 -#define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS, \ - ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS, \ - ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH 1 -#define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS 3 -#define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS, \ - ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS, \ - ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH 1 -#define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS 2 -#define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS, \ - ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS, \ - ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH 1 -#define ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS 1 -#define ADS114S0X_REGISTER_STATUS_FL_REF_L1_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS, \ - ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_REF_L1_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS, \ - ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH 1 -#define ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS 0 -#define ADS114S0X_REGISTER_STATUS_FL_REF_L0_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS, \ - ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH) -#define ADS114S0X_REGISTER_STATUS_FL_REF_L0_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS, \ - ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH) -#define ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH 4 -#define ADS114S0X_REGISTER_INPMUX_MUXP_POS 4 -#define ADS114S0X_REGISTER_INPMUX_MUXP_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_INPMUX_MUXP_POS, \ - ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH) -#define ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_INPMUX_MUXP_POS, \ - ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH) -#define ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH 4 -#define ADS114S0X_REGISTER_INPMUX_MUXN_POS 0 -#define ADS114S0X_REGISTER_INPMUX_MUXN_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_INPMUX_MUXN_POS, \ - ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH) -#define ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_INPMUX_MUXN_POS, \ - ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH) -#define ADS114S0X_REGISTER_PGA_DELAY_LENGTH 3 -#define ADS114S0X_REGISTER_PGA_DELAY_POS 5 -#define ADS114S0X_REGISTER_PGA_DELAY_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_DELAY_POS, \ - ADS114S0X_REGISTER_PGA_DELAY_LENGTH) -#define ADS114S0X_REGISTER_PGA_DELAY_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_DELAY_POS, \ - ADS114S0X_REGISTER_PGA_DELAY_LENGTH) -#define ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH 2 -#define ADS114S0X_REGISTER_PGA_PGA_EN_POS 3 -#define ADS114S0X_REGISTER_PGA_PGA_EN_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_PGA_EN_POS, \ - ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH) -#define ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_PGA_EN_POS, \ - ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH) -#define ADS114S0X_REGISTER_PGA_GAIN_LENGTH 3 -#define ADS114S0X_REGISTER_PGA_GAIN_POS 0 -#define ADS114S0X_REGISTER_PGA_GAIN_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_GAIN_POS, \ - ADS114S0X_REGISTER_PGA_GAIN_LENGTH) -#define ADS114S0X_REGISTER_PGA_GAIN_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_GAIN_POS, \ - ADS114S0X_REGISTER_PGA_GAIN_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH 1 -#define ADS114S0X_REGISTER_DATARATE_G_CHOP_POS 7 -#define ADS114S0X_REGISTER_DATARATE_G_CHOP_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_G_CHOP_POS, \ - ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_G_CHOP_POS, \ - ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_CLK_LENGTH 1 -#define ADS114S0X_REGISTER_DATARATE_CLK_POS 6 -#define ADS114S0X_REGISTER_DATARATE_CLK_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_CLK_POS, \ - ADS114S0X_REGISTER_DATARATE_CLK_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_CLK_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_CLK_POS, \ - ADS114S0X_REGISTER_DATARATE_CLK_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_MODE_LENGTH 1 -#define ADS114S0X_REGISTER_DATARATE_MODE_POS 5 -#define ADS114S0X_REGISTER_DATARATE_MODE_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_MODE_POS, \ - ADS114S0X_REGISTER_DATARATE_MODE_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_MODE_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_MODE_POS, \ - ADS114S0X_REGISTER_DATARATE_MODE_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH 1 -#define ADS114S0X_REGISTER_DATARATE_FILTER_POS 4 -#define ADS114S0X_REGISTER_DATARATE_FILTER_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_FILTER_POS, \ - ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_FILTER_POS, \ - ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_DR_LENGTH 4 -#define ADS114S0X_REGISTER_DATARATE_DR_POS 0 -#define ADS114S0X_REGISTER_DATARATE_DR_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_DR_POS, \ - ADS114S0X_REGISTER_DATARATE_DR_LENGTH) -#define ADS114S0X_REGISTER_DATARATE_DR_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_DR_POS, \ - ADS114S0X_REGISTER_DATARATE_DR_LENGTH) -#define ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH 2 -#define ADS114S0X_REGISTER_REF_FL_REF_EN_POS 6 -#define ADS114S0X_REGISTER_REF_FL_REF_EN_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_FL_REF_EN_POS, \ - ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH) -#define ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_FL_REF_EN_POS, \ - ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH) -#define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH 1 -#define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS 5 -#define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS, \ - ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH) -#define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS, \ - ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH) -#define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH 1 -#define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS 4 -#define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS, \ - ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH) -#define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS, \ - ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH) -#define ADS114S0X_REGISTER_REF_REFSEL_LENGTH 2 -#define ADS114S0X_REGISTER_REF_REFSEL_POS 2 -#define ADS114S0X_REGISTER_REF_REFSEL_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_REFSEL_POS, \ - ADS114S0X_REGISTER_REF_REFSEL_LENGTH) -#define ADS114S0X_REGISTER_REF_REFSEL_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_REFSEL_POS, \ - ADS114S0X_REGISTER_REF_REFSEL_LENGTH) -#define ADS114S0X_REGISTER_REF_REFCON_LENGTH 2 -#define ADS114S0X_REGISTER_REF_REFCON_POS 0 -#define ADS114S0X_REGISTER_REF_REFCON_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_REFCON_POS, \ - ADS114S0X_REGISTER_REF_REFCON_LENGTH) -#define ADS114S0X_REGISTER_REF_REFCON_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_REFCON_POS, \ - ADS114S0X_REGISTER_REF_REFCON_LENGTH) -#define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH 1 -#define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS 7 -#define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS, \ - ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH) -#define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS, \ - ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH) -#define ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH 1 -#define ADS114S0X_REGISTER_IDACMAG_PSW_POS 6 -#define ADS114S0X_REGISTER_IDACMAG_PSW_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_PSW_POS, \ - ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH) -#define ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_PSW_POS, \ - ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH) -#define ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH 4 -#define ADS114S0X_REGISTER_IDACMAG_IMAG_POS 0 -#define ADS114S0X_REGISTER_IDACMAG_IMAG_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_IMAG_POS, \ - ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH) -#define ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_IMAG_POS, \ - ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH) -#define ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH 4 -#define ADS114S0X_REGISTER_IDACMUX_I2MUX_POS 4 -#define ADS114S0X_REGISTER_IDACMUX_I2MUX_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMUX_I2MUX_POS, \ - ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH) -#define ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I2MUX_POS, \ - ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH) -#define ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH 4 -#define ADS114S0X_REGISTER_IDACMUX_I1MUX_POS 0 -#define ADS114S0X_REGISTER_IDACMUX_I1MUX_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS, \ - ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH) -#define ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS, \ - ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH) -#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH 1 -#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS 7 -#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS, \ - ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH) -#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS, \ - ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH) -#define ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH 4 -#define ADS114S0X_REGISTER_GPIODAT_DIR_POS 4 -#define ADS114S0X_REGISTER_GPIODAT_DIR_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIODAT_DIR_POS, \ - ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH) -#define ADS114S0X_REGISTER_GPIODAT_DIR_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIODAT_DIR_POS, \ - ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH) -#define ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH 4 -#define ADS114S0X_REGISTER_GPIODAT_DAT_POS 0 -#define ADS114S0X_REGISTER_GPIODAT_DAT_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIODAT_DAT_POS, \ - ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH) -#define ADS114S0X_REGISTER_GPIODAT_DAT_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIODAT_DAT_POS, \ - ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH) -#define ADS114S0X_REGISTER_GPIOCON_CON_LENGTH 4 -#define ADS114S0X_REGISTER_GPIOCON_CON_POS 0 -#define ADS114S0X_REGISTER_GPIOCON_CON_GET(value) \ - ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIOCON_CON_POS, \ - ADS114S0X_REGISTER_GPIOCON_CON_LENGTH) -#define ADS114S0X_REGISTER_GPIOCON_CON_SET(target, value) \ - ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIOCON_CON_POS, \ - ADS114S0X_REGISTER_GPIOCON_CON_LENGTH) +#define ADS1X4S0X_REGISTER_ID_DEV_ID_LENGTH 3 +#define ADS1X4S0X_REGISTER_ID_DEV_ID_POS 0 +#define ADS1X4S0X_REGISTER_ID_DEV_ID_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_ID_DEV_ID_POS, \ + ADS1X4S0X_REGISTER_ID_DEV_ID_LENGTH) +#define ADS1X4S0X_REGISTER_ID_DEV_ID_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_ID_DEV_ID_POS, \ + ADS1X4S0X_REGISTER_ID_DEV_ID_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_POR_LENGTH 1 +#define ADS1X4S0X_REGISTER_STATUS_FL_POR_POS 7 +#define ADS1X4S0X_REGISTER_STATUS_FL_POR_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_POR_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_POR_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_POR_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_POR_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_POR_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_NOT_RDY_LENGTH 1 +#define ADS1X4S0X_REGISTER_STATUS_NOT_RDY_POS 6 +#define ADS1X4S0X_REGISTER_STATUS_NOT_RDY_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_NOT_RDY_POS, \ + ADS1X4S0X_REGISTER_STATUS_NOT_RDY_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_NOT_RDY_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_NOT_RDY_POS, \ + ADS1X4S0X_REGISTER_STATUS_NOT_RDY_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH 1 +#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_POS 5 +#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH 1 +#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_POS 4 +#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH 1 +#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_POS 3 +#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH 1 +#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_POS 2 +#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_LENGTH 1 +#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_POS 1 +#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_LENGTH 1 +#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_POS 0 +#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_LENGTH) +#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_POS, \ + ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_LENGTH) +#define ADS1X4S0X_REGISTER_INPMUX_MUXP_LENGTH 4 +#define ADS1X4S0X_REGISTER_INPMUX_MUXP_POS 4 +#define ADS1X4S0X_REGISTER_INPMUX_MUXP_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_INPMUX_MUXP_POS, \ + ADS1X4S0X_REGISTER_INPMUX_MUXP_LENGTH) +#define ADS1X4S0X_REGISTER_INPMUX_MUXP_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_INPMUX_MUXP_POS, \ + ADS1X4S0X_REGISTER_INPMUX_MUXP_LENGTH) +#define ADS1X4S0X_REGISTER_INPMUX_MUXN_LENGTH 4 +#define ADS1X4S0X_REGISTER_INPMUX_MUXN_POS 0 +#define ADS1X4S0X_REGISTER_INPMUX_MUXN_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_INPMUX_MUXN_POS, \ + ADS1X4S0X_REGISTER_INPMUX_MUXN_LENGTH) +#define ADS1X4S0X_REGISTER_INPMUX_MUXN_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_INPMUX_MUXN_POS, \ + ADS1X4S0X_REGISTER_INPMUX_MUXN_LENGTH) +#define ADS1X4S0X_REGISTER_PGA_DELAY_LENGTH 3 +#define ADS1X4S0X_REGISTER_PGA_DELAY_POS 5 +#define ADS1X4S0X_REGISTER_PGA_DELAY_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_PGA_DELAY_POS, \ + ADS1X4S0X_REGISTER_PGA_DELAY_LENGTH) +#define ADS1X4S0X_REGISTER_PGA_DELAY_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_PGA_DELAY_POS, \ + ADS1X4S0X_REGISTER_PGA_DELAY_LENGTH) +#define ADS1X4S0X_REGISTER_PGA_PGA_EN_LENGTH 2 +#define ADS1X4S0X_REGISTER_PGA_PGA_EN_POS 3 +#define ADS1X4S0X_REGISTER_PGA_PGA_EN_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_PGA_PGA_EN_POS, \ + ADS1X4S0X_REGISTER_PGA_PGA_EN_LENGTH) +#define ADS1X4S0X_REGISTER_PGA_PGA_EN_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_PGA_PGA_EN_POS, \ + ADS1X4S0X_REGISTER_PGA_PGA_EN_LENGTH) +#define ADS1X4S0X_REGISTER_PGA_GAIN_LENGTH 3 +#define ADS1X4S0X_REGISTER_PGA_GAIN_POS 0 +#define ADS1X4S0X_REGISTER_PGA_GAIN_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_PGA_GAIN_POS, \ + ADS1X4S0X_REGISTER_PGA_GAIN_LENGTH) +#define ADS1X4S0X_REGISTER_PGA_GAIN_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_PGA_GAIN_POS, \ + ADS1X4S0X_REGISTER_PGA_GAIN_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_G_CHOP_LENGTH 1 +#define ADS1X4S0X_REGISTER_DATARATE_G_CHOP_POS 7 +#define ADS1X4S0X_REGISTER_DATARATE_G_CHOP_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_G_CHOP_POS, \ + ADS1X4S0X_REGISTER_DATARATE_G_CHOP_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_G_CHOP_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_G_CHOP_POS, \ + ADS1X4S0X_REGISTER_DATARATE_G_CHOP_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_CLK_LENGTH 1 +#define ADS1X4S0X_REGISTER_DATARATE_CLK_POS 6 +#define ADS1X4S0X_REGISTER_DATARATE_CLK_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_CLK_POS, \ + ADS1X4S0X_REGISTER_DATARATE_CLK_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_CLK_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_CLK_POS, \ + ADS1X4S0X_REGISTER_DATARATE_CLK_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_MODE_LENGTH 1 +#define ADS1X4S0X_REGISTER_DATARATE_MODE_POS 5 +#define ADS1X4S0X_REGISTER_DATARATE_MODE_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_MODE_POS, \ + ADS1X4S0X_REGISTER_DATARATE_MODE_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_MODE_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_MODE_POS, \ + ADS1X4S0X_REGISTER_DATARATE_MODE_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_FILTER_LENGTH 1 +#define ADS1X4S0X_REGISTER_DATARATE_FILTER_POS 4 +#define ADS1X4S0X_REGISTER_DATARATE_FILTER_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_FILTER_POS, \ + ADS1X4S0X_REGISTER_DATARATE_FILTER_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_FILTER_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_FILTER_POS, \ + ADS1X4S0X_REGISTER_DATARATE_FILTER_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_DR_LENGTH 4 +#define ADS1X4S0X_REGISTER_DATARATE_DR_POS 0 +#define ADS1X4S0X_REGISTER_DATARATE_DR_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_DR_POS, \ + ADS1X4S0X_REGISTER_DATARATE_DR_LENGTH) +#define ADS1X4S0X_REGISTER_DATARATE_DR_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_DR_POS, \ + ADS1X4S0X_REGISTER_DATARATE_DR_LENGTH) +#define ADS1X4S0X_REGISTER_REF_FL_REF_EN_LENGTH 2 +#define ADS1X4S0X_REGISTER_REF_FL_REF_EN_POS 6 +#define ADS1X4S0X_REGISTER_REF_FL_REF_EN_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_FL_REF_EN_POS, \ + ADS1X4S0X_REGISTER_REF_FL_REF_EN_LENGTH) +#define ADS1X4S0X_REGISTER_REF_FL_REF_EN_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_FL_REF_EN_POS, \ + ADS1X4S0X_REGISTER_REF_FL_REF_EN_LENGTH) +#define ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH 1 +#define ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_POS 5 +#define ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_POS, \ + ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH) +#define ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_POS, \ + ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH) +#define ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH 1 +#define ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_POS 4 +#define ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_POS, \ + ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH) +#define ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_POS, \ + ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH) +#define ADS1X4S0X_REGISTER_REF_REFSEL_LENGTH 2 +#define ADS1X4S0X_REGISTER_REF_REFSEL_POS 2 +#define ADS1X4S0X_REGISTER_REF_REFSEL_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_REFSEL_POS, \ + ADS1X4S0X_REGISTER_REF_REFSEL_LENGTH) +#define ADS1X4S0X_REGISTER_REF_REFSEL_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_REFSEL_POS, \ + ADS1X4S0X_REGISTER_REF_REFSEL_LENGTH) +#define ADS1X4S0X_REGISTER_REF_REFCON_LENGTH 2 +#define ADS1X4S0X_REGISTER_REF_REFCON_POS 0 +#define ADS1X4S0X_REGISTER_REF_REFCON_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_REFCON_POS, \ + ADS1X4S0X_REGISTER_REF_REFCON_LENGTH) +#define ADS1X4S0X_REGISTER_REF_REFCON_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_REFCON_POS, \ + ADS1X4S0X_REGISTER_REF_REFCON_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH 1 +#define ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS 7 +#define ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS, \ + ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS, \ + ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMAG_PSW_LENGTH 1 +#define ADS1X4S0X_REGISTER_IDACMAG_PSW_POS 6 +#define ADS1X4S0X_REGISTER_IDACMAG_PSW_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMAG_PSW_POS, \ + ADS1X4S0X_REGISTER_IDACMAG_PSW_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMAG_PSW_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMAG_PSW_POS, \ + ADS1X4S0X_REGISTER_IDACMAG_PSW_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMAG_IMAG_LENGTH 4 +#define ADS1X4S0X_REGISTER_IDACMAG_IMAG_POS 0 +#define ADS1X4S0X_REGISTER_IDACMAG_IMAG_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMAG_IMAG_POS, \ + ADS1X4S0X_REGISTER_IDACMAG_IMAG_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMAG_IMAG_POS, \ + ADS1X4S0X_REGISTER_IDACMAG_IMAG_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMUX_I2MUX_LENGTH 4 +#define ADS1X4S0X_REGISTER_IDACMUX_I2MUX_POS 4 +#define ADS1X4S0X_REGISTER_IDACMUX_I2MUX_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMUX_I2MUX_POS, \ + ADS1X4S0X_REGISTER_IDACMUX_I2MUX_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMUX_I2MUX_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMUX_I2MUX_POS, \ + ADS1X4S0X_REGISTER_IDACMUX_I2MUX_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMUX_I1MUX_LENGTH 4 +#define ADS1X4S0X_REGISTER_IDACMUX_I1MUX_POS 0 +#define ADS1X4S0X_REGISTER_IDACMUX_I1MUX_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMUX_I1MUX_POS, \ + ADS1X4S0X_REGISTER_IDACMUX_I1MUX_LENGTH) +#define ADS1X4S0X_REGISTER_IDACMUX_I1MUX_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMUX_I1MUX_POS, \ + ADS1X4S0X_REGISTER_IDACMUX_I1MUX_LENGTH) +#define ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH 1 +#define ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_POS 7 +#define ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_POS, \ + ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH) +#define ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_POS, \ + ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH) +#define ADS1X4S0X_REGISTER_GPIODAT_DIR_LENGTH 4 +#define ADS1X4S0X_REGISTER_GPIODAT_DIR_POS 4 +#define ADS1X4S0X_REGISTER_GPIODAT_DIR_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_GPIODAT_DIR_POS, \ + ADS1X4S0X_REGISTER_GPIODAT_DIR_LENGTH) +#define ADS1X4S0X_REGISTER_GPIODAT_DIR_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_GPIODAT_DIR_POS, \ + ADS1X4S0X_REGISTER_GPIODAT_DIR_LENGTH) +#define ADS1X4S0X_REGISTER_GPIODAT_DAT_LENGTH 4 +#define ADS1X4S0X_REGISTER_GPIODAT_DAT_POS 0 +#define ADS1X4S0X_REGISTER_GPIODAT_DAT_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_GPIODAT_DAT_POS, \ + ADS1X4S0X_REGISTER_GPIODAT_DAT_LENGTH) +#define ADS1X4S0X_REGISTER_GPIODAT_DAT_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_GPIODAT_DAT_POS, \ + ADS1X4S0X_REGISTER_GPIODAT_DAT_LENGTH) +#define ADS1X4S0X_REGISTER_GPIOCON_CON_LENGTH 4 +#define ADS1X4S0X_REGISTER_GPIOCON_CON_POS 0 +#define ADS1X4S0X_REGISTER_GPIOCON_CON_GET(value) \ + ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_GPIOCON_CON_POS, \ + ADS1X4S0X_REGISTER_GPIOCON_CON_LENGTH) +#define ADS1X4S0X_REGISTER_GPIOCON_CON_SET(target, value) \ + ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_GPIOCON_CON_POS, \ + ADS1X4S0X_REGISTER_GPIOCON_CON_LENGTH) /* * - AIN0 as positive input * - AIN1 as negative input */ -#define ADS114S0X_REGISTER_INPMUX_SET_DEFAULTS(target) \ - ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, 0b0000); \ - ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, 0b0001) +#define ADS1X4S0X_REGISTER_INPMUX_SET_DEFAULTS(target) \ + ADS1X4S0X_REGISTER_INPMUX_MUXP_SET(target, 0b0000); \ + ADS1X4S0X_REGISTER_INPMUX_MUXN_SET(target, 0b0001) /* * - disable reference monitor * - enable positive reference buffer @@ -366,12 +366,12 @@ enum ads114s0x_register { * - use internal reference * - enable internal voltage reference */ -#define ADS114S0X_REGISTER_REF_SET_DEFAULTS(target) \ - ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, 0b00); \ - ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, 0b0); \ - ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, 0b1); \ - ADS114S0X_REGISTER_REF_REFSEL_SET(target, 0b10); \ - ADS114S0X_REGISTER_REF_REFCON_SET(target, 0b01) +#define ADS1X4S0X_REGISTER_REF_SET_DEFAULTS(target) \ + ADS1X4S0X_REGISTER_REF_FL_REF_EN_SET(target, 0b00); \ + ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, 0b0); \ + ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, 0b1); \ + ADS1X4S0X_REGISTER_REF_REFSEL_SET(target, 0b10); \ + ADS1X4S0X_REGISTER_REF_REFCON_SET(target, 0b01) /* * - disable global chop * - use internal oscillator @@ -379,39 +379,39 @@ enum ads114s0x_register { * - low latency filter * - 20 samples per second */ -#define ADS114S0X_REGISTER_DATARATE_SET_DEFAULTS(target) \ - ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, 0b0); \ - ADS114S0X_REGISTER_DATARATE_CLK_SET(target, 0b0); \ - ADS114S0X_REGISTER_DATARATE_MODE_SET(target, 0b1); \ - ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, 0b1); \ - ADS114S0X_REGISTER_DATARATE_DR_SET(target, 0b0100) +#define ADS1X4S0X_REGISTER_DATARATE_SET_DEFAULTS(target) \ + ADS1X4S0X_REGISTER_DATARATE_G_CHOP_SET(target, 0b0); \ + ADS1X4S0X_REGISTER_DATARATE_CLK_SET(target, 0b0); \ + ADS1X4S0X_REGISTER_DATARATE_MODE_SET(target, 0b1); \ + ADS1X4S0X_REGISTER_DATARATE_FILTER_SET(target, 0b1); \ + ADS1X4S0X_REGISTER_DATARATE_DR_SET(target, 0b0100) /* * - delay of 14*t_mod * - disable gain * - gain 1 */ -#define ADS114S0X_REGISTER_PGA_SET_DEFAULTS(target) \ - ADS114S0X_REGISTER_PGA_DELAY_SET(target, 0b000); \ - ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, 0b00); \ - ADS114S0X_REGISTER_PGA_GAIN_SET(target, 0b000) +#define ADS1X4S0X_REGISTER_PGA_SET_DEFAULTS(target) \ + ADS1X4S0X_REGISTER_PGA_DELAY_SET(target, 0b000); \ + ADS1X4S0X_REGISTER_PGA_PGA_EN_SET(target, 0b00); \ + ADS1X4S0X_REGISTER_PGA_GAIN_SET(target, 0b000) /* * - disable PGA output rail flag * - low-side power switch * - IDAC off */ -#define ADS114S0X_REGISTER_IDACMAG_SET_DEFAULTS(target) \ - ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, 0b0); \ - ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, 0b0); \ - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, 0b0000) +#define ADS1X4S0X_REGISTER_IDACMAG_SET_DEFAULTS(target) \ + ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, 0b0); \ + ADS1X4S0X_REGISTER_IDACMAG_PSW_SET(target, 0b0); \ + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(target, 0b0000) /* * - disconnect IDAC1 * - disconnect IDAC2 */ -#define ADS114S0X_REGISTER_IDACMUX_SET_DEFAULTS(target) \ - ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, 0b1111); \ - ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, 0b1111) +#define ADS1X4S0X_REGISTER_IDACMUX_SET_DEFAULTS(target) \ + ADS1X4S0X_REGISTER_IDACMUX_I1MUX_SET(target, 0b1111); \ + ADS1X4S0X_REGISTER_IDACMUX_I2MUX_SET(target, 0b1111) -struct ads114s0x_config { +struct ads1x4s0x_config { struct spi_dt_spec bus; #if CONFIG_ADC_ASYNC k_thread_stack_t *stack; @@ -423,7 +423,7 @@ struct ads114s0x_config { uint8_t vbias_level; }; -struct ads114s0x_data { +struct ads1x4s0x_data { struct adc_context ctx; #if CONFIG_ADC_ASYNC struct k_thread thread; @@ -433,30 +433,30 @@ struct ads114s0x_data { struct k_sem acquire_signal; int16_t *buffer; int16_t *buffer_ptr; -#if CONFIG_ADC_ADS114S0X_GPIO +#if CONFIG_ADC_ADS1X4S0X_GPIO struct k_mutex gpio_lock; uint8_t gpio_enabled; /* one bit per GPIO, 1 = enabled */ uint8_t gpio_direction; /* one bit per GPIO, 1 = input */ uint8_t gpio_value; /* one bit per GPIO, 1 = high */ -#endif /* CONFIG_ADC_ADS114S0X_GPIO */ +#endif /* CONFIG_ADC_ADS1X4S0X_GPIO */ }; -static void ads114s0x_data_ready_handler(const struct device *dev, struct gpio_callback *gpio_cb, +static void ads1x4s0x_data_ready_handler(const struct device *dev, struct gpio_callback *gpio_cb, uint32_t pins) { ARG_UNUSED(dev); ARG_UNUSED(pins); - struct ads114s0x_data *data = - CONTAINER_OF(gpio_cb, struct ads114s0x_data, callback_data_ready); + struct ads1x4s0x_data *data = + CONTAINER_OF(gpio_cb, struct ads1x4s0x_data, callback_data_ready); k_sem_give(&data->data_ready_signal); } -static int ads114s0x_read_register(const struct device *dev, - enum ads114s0x_register register_address, uint8_t *value) +static int ads1x4s0x_read_register(const struct device *dev, + enum ads1x4s0x_register register_address, uint8_t *value) { - const struct ads114s0x_config *config = dev->config; + const struct ads1x4s0x_config *config = dev->config; uint8_t buffer_tx[3]; uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)]; const struct spi_buf tx_buf[] = {{ @@ -476,7 +476,7 @@ static int ads114s0x_read_register(const struct device *dev, .count = ARRAY_SIZE(rx_buf), }; - buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_RREG) | ((uint8_t)register_address); + buffer_tx[0] = ((uint8_t)ADS1X4S0X_COMMAND_RREG) | ((uint8_t)register_address); /* read one register */ buffer_tx[1] = 0x00; @@ -493,10 +493,10 @@ static int ads114s0x_read_register(const struct device *dev, return 0; } -static int ads114s0x_write_register(const struct device *dev, - enum ads114s0x_register register_address, uint8_t value) +static int ads1x4s0x_write_register(const struct device *dev, + enum ads1x4s0x_register register_address, uint8_t value) { - const struct ads114s0x_config *config = dev->config; + const struct ads1x4s0x_config *config = dev->config; uint8_t buffer_tx[3]; const struct spi_buf tx_buf[] = {{ .buf = buffer_tx, @@ -507,7 +507,7 @@ static int ads114s0x_write_register(const struct device *dev, .count = ARRAY_SIZE(tx_buf), }; - buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_address); + buffer_tx[0] = ((uint8_t)ADS1X4S0X_COMMAND_WREG) | ((uint8_t)register_address); /* write one register */ buffer_tx[1] = 0x00; buffer_tx[2] = value; @@ -523,11 +523,11 @@ static int ads114s0x_write_register(const struct device *dev, return 0; } -static int ads114s0x_write_multiple_registers(const struct device *dev, - enum ads114s0x_register *register_addresses, +static int ads1x4s0x_write_multiple_registers(const struct device *dev, + enum ads1x4s0x_register *register_addresses, uint8_t *values, size_t count) { - const struct ads114s0x_config *config = dev->config; + const struct ads1x4s0x_config *config = dev->config; uint8_t buffer_tx[2]; const struct spi_buf tx_buf[] = { { @@ -549,7 +549,7 @@ static int ads114s0x_write_multiple_registers(const struct device *dev, return -EINVAL; } - buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_addresses[0]); + buffer_tx[0] = ((uint8_t)ADS1X4S0X_COMMAND_WREG) | ((uint8_t)register_addresses[0]); buffer_tx[1] = count - 1; LOG_HEXDUMP_DBG(register_addresses, count, "writing to registers"); @@ -571,9 +571,9 @@ static int ads114s0x_write_multiple_registers(const struct device *dev, return 0; } -static int ads114s0x_send_command(const struct device *dev, enum ads114s0x_command command) +static int ads1x4s0x_send_command(const struct device *dev, enum ads1x4s0x_command command) { - const struct ads114s0x_config *config = dev->config; + const struct ads1x4s0x_config *config = dev->config; uint8_t buffer_tx[1]; const struct spi_buf tx_buf[] = {{ .buf = buffer_tx, @@ -597,10 +597,10 @@ static int ads114s0x_send_command(const struct device *dev, enum ads114s0x_comma return 0; } -static int ads114s0x_channel_setup(const struct device *dev, +static int ads1x4s0x_channel_setup(const struct device *dev, const struct adc_channel_cfg *channel_cfg) { - const struct ads114s0x_config *config = dev->config; + const struct ads1x4s0x_config *config = dev->config; uint8_t input_mux = 0; uint8_t reference_control = 0; uint8_t data_rate = 0; @@ -611,17 +611,17 @@ static int ads114s0x_channel_setup(const struct device *dev, uint8_t vbias = 0; size_t pin_selections_size; int result; - enum ads114s0x_register register_addresses[7]; + enum ads1x4s0x_register register_addresses[7]; uint8_t values[ARRAY_SIZE(register_addresses)]; uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time); uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time); - ADS114S0X_REGISTER_INPMUX_SET_DEFAULTS(gain); - ADS114S0X_REGISTER_REF_SET_DEFAULTS(reference_control); - ADS114S0X_REGISTER_DATARATE_SET_DEFAULTS(data_rate); - ADS114S0X_REGISTER_PGA_SET_DEFAULTS(gain); - ADS114S0X_REGISTER_IDACMAG_SET_DEFAULTS(idac_magnitude); - ADS114S0X_REGISTER_IDACMUX_SET_DEFAULTS(idac_mux); + ADS1X4S0X_REGISTER_INPMUX_SET_DEFAULTS(gain); + ADS1X4S0X_REGISTER_REF_SET_DEFAULTS(reference_control); + ADS1X4S0X_REGISTER_DATARATE_SET_DEFAULTS(data_rate); + ADS1X4S0X_REGISTER_PGA_SET_DEFAULTS(gain); + ADS1X4S0X_REGISTER_IDACMAG_SET_DEFAULTS(idac_magnitude); + ADS1X4S0X_REGISTER_IDACMUX_SET_DEFAULTS(idac_mux); if (channel_cfg->channel_id != 0) { LOG_ERR("%s: only one channel is supported", dev->name); @@ -641,35 +641,35 @@ static int ads114s0x_channel_setup(const struct device *dev, } if (channel_cfg->acquisition_time == ADC_ACQ_TIME_DEFAULT) { - ADS114S0X_REGISTER_DATARATE_DR_SET(data_rate, ADS114S0X_CONFIG_DR_20); + ADS1X4S0X_REGISTER_DATARATE_DR_SET(data_rate, ADS1X4S0X_CONFIG_DR_20); } else { - ADS114S0X_REGISTER_DATARATE_DR_SET(data_rate, acquisition_time_value); + ADS1X4S0X_REGISTER_DATARATE_DR_SET(data_rate, acquisition_time_value); } switch (channel_cfg->reference) { case ADC_REF_INTERNAL: /* disable negative reference buffer */ - ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b1); + ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b1); /* disable positive reference buffer */ - ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b1); + ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b1); /* use internal reference */ - ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b10); + ADS1X4S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b10); break; case ADC_REF_EXTERNAL0: /* enable negative reference buffer */ - ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0); + ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0); /* enable positive reference buffer */ - ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0); + ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0); /* use external reference 0*/ - ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b00); + ADS1X4S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b00); break; case ADC_REF_EXTERNAL1: /* enable negative reference buffer */ - ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0); + ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0); /* enable positive reference buffer */ - ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0); + ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0); /* use external reference 0*/ - ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b01); + ADS1X4S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b01); break; default: LOG_ERR("%s: reference %i is not supported", dev->name, channel_cfg->reference); @@ -680,13 +680,13 @@ static int ads114s0x_channel_setup(const struct device *dev, LOG_DBG("%s: configuring channel for a differential measurement from the pins (p, " "n) (%i, %i)", dev->name, channel_cfg->input_positive, channel_cfg->input_negative); - if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) { + if (channel_cfg->input_positive >= ADS1X4S0X_INPUT_SELECTION_AINCOM) { LOG_ERR("%s: positive channel input %i is invalid", dev->name, channel_cfg->input_positive); return -EINVAL; } - if (channel_cfg->input_negative >= ADS114S0X_INPUT_SELECTION_AINCOM) { + if (channel_cfg->input_negative >= ADS1X4S0X_INPUT_SELECTION_AINCOM) { LOG_ERR("%s: negative channel input %i is invalid", dev->name, channel_cfg->input_negative); return -EINVAL; @@ -698,50 +698,50 @@ static int ads114s0x_channel_setup(const struct device *dev, return -EINVAL; } - ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive); - ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, channel_cfg->input_negative); + ADS1X4S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive); + ADS1X4S0X_REGISTER_INPMUX_MUXN_SET(input_mux, channel_cfg->input_negative); pin_selections[0] = channel_cfg->input_positive; pin_selections[1] = channel_cfg->input_negative; } else { LOG_DBG("%s: configuring channel for single ended measurement from input %i", dev->name, channel_cfg->input_positive); - if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) { + if (channel_cfg->input_positive >= ADS1X4S0X_INPUT_SELECTION_AINCOM) { LOG_ERR("%s: channel input %i is invalid", dev->name, channel_cfg->input_positive); return -EINVAL; } - ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive); - ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, ADS114S0X_INPUT_SELECTION_AINCOM); + ADS1X4S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive); + ADS1X4S0X_REGISTER_INPMUX_MUXN_SET(input_mux, ADS1X4S0X_INPUT_SELECTION_AINCOM); pin_selections[0] = channel_cfg->input_positive; - pin_selections[1] = ADS114S0X_INPUT_SELECTION_AINCOM; + pin_selections[1] = ADS1X4S0X_INPUT_SELECTION_AINCOM; } switch (channel_cfg->gain) { case ADC_GAIN_1: /* set gain value */ - ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b000); + ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b000); break; case ADC_GAIN_2: - ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b001); + ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b001); break; case ADC_GAIN_4: - ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b010); + ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b010); break; case ADC_GAIN_8: - ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b011); + ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b011); break; case ADC_GAIN_16: - ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b100); + ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b100); break; case ADC_GAIN_32: - ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b101); + ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b101); break; case ADC_GAIN_64: - ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b110); + ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b110); break; case ADC_GAIN_128: - ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b111); + ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b111); break; default: LOG_ERR("%s: gain value %i not supported", dev->name, channel_cfg->gain); @@ -750,39 +750,39 @@ static int ads114s0x_channel_setup(const struct device *dev, if (channel_cfg->gain != ADC_GAIN_1) { /* enable gain */ - ADS114S0X_REGISTER_PGA_PGA_EN_SET(gain, 0b01); + ADS1X4S0X_REGISTER_PGA_PGA_EN_SET(gain, 0b01); } switch (config->idac_current) { case 0: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0000); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0000); break; case 10: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0001); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0001); break; case 50: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0010); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0010); break; case 100: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0011); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0011); break; case 250: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0100); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0100); break; case 500: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0101); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0101); break; case 750: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0110); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0110); break; case 1000: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0111); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0111); break; case 1500: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1000); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1000); break; case 2000: - ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1001); + ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1001); break; default: LOG_ERR("%s: IDAC magnitude %i not supported", dev->name, config->idac_current); @@ -804,8 +804,8 @@ static int ads114s0x_channel_setup(const struct device *dev, return -EINVAL; } - ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(idac_mux, channel_cfg->current_source_pin[0]); - ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(idac_mux, channel_cfg->current_source_pin[1]); + ADS1X4S0X_REGISTER_IDACMUX_I1MUX_SET(idac_mux, channel_cfg->current_source_pin[0]); + ADS1X4S0X_REGISTER_IDACMUX_I2MUX_SET(idac_mux, channel_cfg->current_source_pin[1]); pin_selections[2] = channel_cfg->current_source_pin[0]; pin_selections[3] = channel_cfg->current_source_pin[1]; pin_selections_size = 4; @@ -815,12 +815,12 @@ static int ads114s0x_channel_setup(const struct device *dev, } for (size_t i = 0; i < pin_selections_size; ++i) { - if (pin_selections[i] > ADS114S0X_INPUT_SELECTION_AINCOM) { + if (pin_selections[i] > ADS1X4S0X_INPUT_SELECTION_AINCOM) { continue; } for (size_t j = i + 1; j < pin_selections_size; ++j) { - if (pin_selections[j] > ADS114S0X_INPUT_SELECTION_AINCOM) { + if (pin_selections[j] > ADS1X4S0X_INPUT_SELECTION_AINCOM) { continue; } @@ -832,10 +832,10 @@ static int ads114s0x_channel_setup(const struct device *dev, } } - ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(vbias, config->vbias_level); + ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_SET(vbias, config->vbias_level); if ((channel_cfg->vbias_pins & - ~GENMASK(ADS114S0X_VBIAS_PIN_MAX, ADS114S0X_VBIAS_PIN_MIN)) != 0) { + ~GENMASK(ADS1X4S0X_VBIAS_PIN_MAX, ADS1X4S0X_VBIAS_PIN_MIN)) != 0) { LOG_ERR("%s: invalid VBIAS pin selection 0x%08X", dev->name, channel_cfg->vbias_pins); return -EINVAL; @@ -843,13 +843,13 @@ static int ads114s0x_channel_setup(const struct device *dev, vbias |= channel_cfg->vbias_pins; - register_addresses[0] = ADS114S0X_REGISTER_INPMUX; - register_addresses[1] = ADS114S0X_REGISTER_PGA; - register_addresses[2] = ADS114S0X_REGISTER_DATARATE; - register_addresses[3] = ADS114S0X_REGISTER_REF; - register_addresses[4] = ADS114S0X_REGISTER_IDACMAG; - register_addresses[5] = ADS114S0X_REGISTER_IDACMUX; - register_addresses[6] = ADS114S0X_REGISTER_VBIAS; + register_addresses[0] = ADS1X4S0X_REGISTER_INPMUX; + register_addresses[1] = ADS1X4S0X_REGISTER_PGA; + register_addresses[2] = ADS1X4S0X_REGISTER_DATARATE; + register_addresses[3] = ADS1X4S0X_REGISTER_REF; + register_addresses[4] = ADS1X4S0X_REGISTER_IDACMAG; + register_addresses[5] = ADS1X4S0X_REGISTER_IDACMUX; + register_addresses[6] = ADS1X4S0X_REGISTER_VBIAS; BUILD_ASSERT(ARRAY_SIZE(register_addresses) == 7); values[0] = input_mux; values[1] = gain; @@ -860,7 +860,7 @@ static int ads114s0x_channel_setup(const struct device *dev, values[6] = vbias; BUILD_ASSERT(ARRAY_SIZE(values) == 7); - result = ads114s0x_write_multiple_registers(dev, register_addresses, values, + result = ads1x4s0x_write_multiple_registers(dev, register_addresses, values, ARRAY_SIZE(values)); if (result != 0) { @@ -871,7 +871,7 @@ static int ads114s0x_channel_setup(const struct device *dev, return 0; } -static int ads114s0x_validate_buffer_size(const struct adc_sequence *sequence) +static int ads1x4s0x_validate_buffer_size(const struct adc_sequence *sequence) { size_t needed = sizeof(int16_t); @@ -886,10 +886,10 @@ static int ads114s0x_validate_buffer_size(const struct adc_sequence *sequence) return 0; } -static int ads114s0x_validate_sequence(const struct device *dev, +static int ads1x4s0x_validate_sequence(const struct device *dev, const struct adc_sequence *sequence) { - if (sequence->resolution != ADS114S0X_RESOLUTION) { + if (sequence->resolution != ADS1X4S0X_RESOLUTION) { LOG_ERR("%s: invalid resolution", dev->name); return -EINVAL; } @@ -904,12 +904,12 @@ static int ads114s0x_validate_sequence(const struct device *dev, return -EINVAL; } - return ads114s0x_validate_buffer_size(sequence); + return ads1x4s0x_validate_buffer_size(sequence); } static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling) { - struct ads114s0x_data *data = CONTAINER_OF(ctx, struct ads114s0x_data, ctx); + struct ads1x4s0x_data *data = CONTAINER_OF(ctx, struct ads1x4s0x_data, ctx); if (repeat_sampling) { data->buffer = data->buffer_ptr; @@ -918,19 +918,19 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repe static void adc_context_start_sampling(struct adc_context *ctx) { - struct ads114s0x_data *data = CONTAINER_OF(ctx, struct ads114s0x_data, ctx); + struct ads1x4s0x_data *data = CONTAINER_OF(ctx, struct ads1x4s0x_data, ctx); data->buffer_ptr = data->buffer; k_sem_give(&data->acquire_signal); } -static int ads114s0x_adc_start_read(const struct device *dev, const struct adc_sequence *sequence, +static int ads1x4s0x_adc_start_read(const struct device *dev, const struct adc_sequence *sequence, bool wait) { int result; - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; - result = ads114s0x_validate_sequence(dev, sequence); + result = ads1x4s0x_validate_sequence(dev, sequence); if (result != 0) { LOG_ERR("%s: sequence validation failed", dev->name); @@ -948,13 +948,13 @@ static int ads114s0x_adc_start_read(const struct device *dev, const struct adc_s return result; } -static int ads114s0x_send_start_read(const struct device *dev) +static int ads1x4s0x_send_start_read(const struct device *dev) { - const struct ads114s0x_config *config = dev->config; + const struct ads1x4s0x_config *config = dev->config; int result; if (config->gpio_start_sync.port == 0) { - result = ads114s0x_send_command(dev, ADS114S0X_COMMAND_START); + result = ads1x4s0x_send_command(dev, ADS1X4S0X_COMMAND_START); if (result != 0) { LOG_ERR("%s: unable to send START/SYNC command", dev->name); return result; @@ -967,8 +967,8 @@ static int ads114s0x_send_start_read(const struct device *dev) return result; } - k_sleep(K_USEC(ADS114S0X_START_SYNC_PULSE_DURATION_IN_US + - ADS114S0X_SETUP_TIME_IN_US)); + k_sleep(K_USEC(ADS1X4S0X_START_SYNC_PULSE_DURATION_IN_US + + ADS1X4S0X_SETUP_TIME_IN_US)); result = gpio_pin_set_dt(&config->gpio_start_sync, 0); @@ -981,16 +981,16 @@ static int ads114s0x_send_start_read(const struct device *dev) return 0; } -static int ads114s0x_wait_data_ready(const struct device *dev) +static int ads1x4s0x_wait_data_ready(const struct device *dev) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; return k_sem_take(&data->data_ready_signal, ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT); } -static int ads114s0x_read_sample(const struct device *dev, uint16_t *buffer) +static int ads1x4s0x_read_sample(const struct device *dev, uint16_t *buffer) { - const struct ads114s0x_config *config = dev->config; + const struct ads1x4s0x_config *config = dev->config; uint8_t buffer_tx[3]; uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)]; const struct spi_buf tx_buf[] = {{ @@ -1010,7 +1010,7 @@ static int ads114s0x_read_sample(const struct device *dev, uint16_t *buffer) .count = ARRAY_SIZE(rx_buf), }; - buffer_tx[0] = (uint8_t)ADS114S0X_COMMAND_RDATA; + buffer_tx[0] = (uint8_t)ADS1X4S0X_COMMAND_RDATA; int result = spi_transceive_dt(&config->bus, &tx, &rx); @@ -1025,29 +1025,29 @@ static int ads114s0x_read_sample(const struct device *dev, uint16_t *buffer) return 0; } -static int ads114s0x_adc_perform_read(const struct device *dev) +static int ads1x4s0x_adc_perform_read(const struct device *dev) { int result; - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; k_sem_take(&data->acquire_signal, K_FOREVER); k_sem_reset(&data->data_ready_signal); - result = ads114s0x_send_start_read(dev); + result = ads1x4s0x_send_start_read(dev); if (result != 0) { LOG_ERR("%s: unable to start ADC conversion", dev->name); adc_context_complete(&data->ctx, result); return result; } - result = ads114s0x_wait_data_ready(dev); + result = ads1x4s0x_wait_data_ready(dev); if (result != 0) { LOG_ERR("%s: waiting for data to be ready failed", dev->name); adc_context_complete(&data->ctx, result); return result; } - result = ads114s0x_read_sample(dev, data->buffer); + result = ads1x4s0x_read_sample(dev, data->buffer); if (result != 0) { LOG_ERR("%s: reading sample failed", dev->name); adc_context_complete(&data->ctx, result); @@ -1062,42 +1062,42 @@ static int ads114s0x_adc_perform_read(const struct device *dev) } #if CONFIG_ADC_ASYNC -static int ads114s0x_adc_read_async(const struct device *dev, const struct adc_sequence *sequence, +static int ads1x4s0x_adc_read_async(const struct device *dev, const struct adc_sequence *sequence, struct k_poll_signal *async) { int result; - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; adc_context_lock(&data->ctx, true, async); - result = ads114s0x_adc_start_read(dev, sequence, true); + result = ads1x4s0x_adc_start_read(dev, sequence, true); adc_context_release(&data->ctx, result); return result; } -static int ads114s0x_read(const struct device *dev, const struct adc_sequence *sequence) +static int ads1x4s0x_read(const struct device *dev, const struct adc_sequence *sequence) { int result; - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; adc_context_lock(&data->ctx, false, NULL); - result = ads114s0x_adc_start_read(dev, sequence, true); + result = ads1x4s0x_adc_start_read(dev, sequence, true); adc_context_release(&data->ctx, result); return result; } #else -static int ads114s0x_read(const struct device *dev, const struct adc_sequence *sequence) +static int ads1x4s0x_read(const struct device *dev, const struct adc_sequence *sequence) { int result; - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; adc_context_lock(&data->ctx, false, NULL); - result = ads114s0x_adc_start_read(dev, sequence, false); + result = ads1x4s0x_adc_start_read(dev, sequence, false); while (result == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) { - result = ads114s0x_adc_perform_read(dev); + result = ads1x4s0x_adc_perform_read(dev); } adc_context_release(&data->ctx, result); @@ -1106,56 +1106,56 @@ static int ads114s0x_read(const struct device *dev, const struct adc_sequence *s #endif #if CONFIG_ADC_ASYNC -static void ads114s0x_acquisition_thread(void *p1, void *p2, void *p3) +static void ads1x4s0x_acquisition_thread(void *p1, void *p2, void *p3) { ARG_UNUSED(p2); ARG_UNUSED(p3); const struct device *dev = p1; while (true) { - ads114s0x_adc_perform_read(dev); + ads1x4s0x_adc_perform_read(dev); } } #endif -#ifdef CONFIG_ADC_ADS114S0X_GPIO -static int ads114s0x_gpio_write_config(const struct device *dev) +#ifdef CONFIG_ADC_ADS1X4S0X_GPIO +static int ads1x4s0x_gpio_write_config(const struct device *dev) { - struct ads114s0x_data *data = dev->data; - enum ads114s0x_register register_addresses[2]; + struct ads1x4s0x_data *data = dev->data; + enum ads1x4s0x_register register_addresses[2]; uint8_t register_values[ARRAY_SIZE(register_addresses)]; uint8_t gpio_dat = 0; uint8_t gpio_con = 0; - ADS114S0X_REGISTER_GPIOCON_CON_SET(gpio_con, data->gpio_enabled); - ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value); - ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction); + ADS1X4S0X_REGISTER_GPIOCON_CON_SET(gpio_con, data->gpio_enabled); + ADS1X4S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value); + ADS1X4S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction); register_values[0] = gpio_dat; register_values[1] = gpio_con; - register_addresses[0] = ADS114S0X_REGISTER_GPIODAT; - register_addresses[1] = ADS114S0X_REGISTER_GPIOCON; - return ads114s0x_write_multiple_registers(dev, register_addresses, register_values, + register_addresses[0] = ADS1X4S0X_REGISTER_GPIODAT; + register_addresses[1] = ADS1X4S0X_REGISTER_GPIOCON; + return ads1x4s0x_write_multiple_registers(dev, register_addresses, register_values, ARRAY_SIZE(register_values)); } -static int ads114s0x_gpio_write_value(const struct device *dev) +static int ads1x4s0x_gpio_write_value(const struct device *dev) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; uint8_t gpio_dat = 0; - ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value); - ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction); + ADS1X4S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value); + ADS1X4S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction); - return ads114s0x_write_register(dev, ADS114S0X_REGISTER_GPIODAT, gpio_dat); + return ads1x4s0x_write_register(dev, ADS1X4S0X_REGISTER_GPIODAT, gpio_dat); } -int ads114s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value) +int ads1x4s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; int result = 0; - if (pin > ADS114S0X_GPIO_MAX) { + if (pin > ADS1X4S0X_GPIO_MAX) { LOG_ERR("%s: invalid pin %i", dev->name, pin); return -EINVAL; } @@ -1171,19 +1171,19 @@ int ads114s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initia data->gpio_value &= ~BIT(pin); } - result = ads114s0x_gpio_write_config(dev); + result = ads1x4s0x_gpio_write_config(dev); k_mutex_unlock(&data->gpio_lock); return result; } -int ads114s0x_gpio_set_input(const struct device *dev, uint8_t pin) +int ads1x4s0x_gpio_set_input(const struct device *dev, uint8_t pin) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; int result = 0; - if (pin > ADS114S0X_GPIO_MAX) { + if (pin > ADS1X4S0X_GPIO_MAX) { LOG_ERR("%s: invalid pin %i", dev->name, pin); return -EINVAL; } @@ -1194,19 +1194,19 @@ int ads114s0x_gpio_set_input(const struct device *dev, uint8_t pin) data->gpio_direction |= BIT(pin); data->gpio_value &= ~BIT(pin); - result = ads114s0x_gpio_write_config(dev); + result = ads1x4s0x_gpio_write_config(dev); k_mutex_unlock(&data->gpio_lock); return result; } -int ads114s0x_gpio_deconfigure(const struct device *dev, uint8_t pin) +int ads1x4s0x_gpio_deconfigure(const struct device *dev, uint8_t pin) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; int result = 0; - if (pin > ADS114S0X_GPIO_MAX) { + if (pin > ADS1X4S0X_GPIO_MAX) { LOG_ERR("%s: invalid pin %i", dev->name, pin); return -EINVAL; } @@ -1217,19 +1217,19 @@ int ads114s0x_gpio_deconfigure(const struct device *dev, uint8_t pin) data->gpio_direction |= BIT(pin); data->gpio_value &= ~BIT(pin); - result = ads114s0x_gpio_write_config(dev); + result = ads1x4s0x_gpio_write_config(dev); k_mutex_unlock(&data->gpio_lock); return result; } -int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool value) +int ads1x4s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool value) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; int result = 0; - if (pin > ADS114S0X_GPIO_MAX) { + if (pin > ADS1X4S0X_GPIO_MAX) { LOG_ERR("%s: invalid pin %i", dev->name, pin); return -EINVAL; } @@ -1245,7 +1245,7 @@ int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool val } else { data->gpio_value |= BIT(pin); - result = ads114s0x_gpio_write_value(dev); + result = ads1x4s0x_gpio_write_value(dev); } k_mutex_unlock(&data->gpio_lock); @@ -1253,13 +1253,13 @@ int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool val return result; } -int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *value) +int ads1x4s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *value) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; int result = 0; uint8_t gpio_dat; - if (pin > ADS114S0X_GPIO_MAX) { + if (pin > ADS1X4S0X_GPIO_MAX) { LOG_ERR("%s: invalid pin %i", dev->name, pin); return -EINVAL; } @@ -1273,8 +1273,8 @@ int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *va LOG_ERR("%s: gpio pin %i not configured as input", dev->name, pin); result = -EINVAL; } else { - result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_GPIODAT, &gpio_dat); - data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat); + result = ads1x4s0x_read_register(dev, ADS1X4S0X_REGISTER_GPIODAT, &gpio_dat); + data->gpio_value = ADS1X4S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat); *value = (BIT(pin) & data->gpio_value) != 0; } @@ -1283,16 +1283,16 @@ int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *va return result; } -int ads114s0x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value) +int ads1x4s0x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; int result = 0; uint8_t gpio_dat; k_mutex_lock(&data->gpio_lock, K_FOREVER); - result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_GPIODAT, &gpio_dat); - data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat); + result = ads1x4s0x_read_register(dev, ADS1X4S0X_REGISTER_GPIODAT, &gpio_dat); + data->gpio_value = ADS1X4S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat); *value = data->gpio_value; k_mutex_unlock(&data->gpio_lock); @@ -1300,57 +1300,57 @@ int ads114s0x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *val return result; } -int ads114s0x_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, +int ads1x4s0x_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, gpio_port_value_t value) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; int result = 0; k_mutex_lock(&data->gpio_lock, K_FOREVER); data->gpio_value = ((data->gpio_value & ~mask) | (mask & value)) & data->gpio_enabled & ~data->gpio_direction; - result = ads114s0x_gpio_write_value(dev); + result = ads1x4s0x_gpio_write_value(dev); k_mutex_unlock(&data->gpio_lock); return result; } -int ads114s0x_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +int ads1x4s0x_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) { - struct ads114s0x_data *data = dev->data; + struct ads1x4s0x_data *data = dev->data; int result = 0; k_mutex_lock(&data->gpio_lock, K_FOREVER); data->gpio_value = (data->gpio_value ^ pins) & data->gpio_enabled & ~data->gpio_direction; - result = ads114s0x_gpio_write_value(dev); + result = ads1x4s0x_gpio_write_value(dev); k_mutex_unlock(&data->gpio_lock); return result; } -#endif /* CONFIG_ADC_ADS114S0X_GPIO */ +#endif /* CONFIG_ADC_ADS1X4S0X_GPIO */ -static int ads114s0x_init(const struct device *dev) +static int ads1x4s0x_init(const struct device *dev) { uint8_t status = 0; uint8_t reference_control = 0; uint8_t reference_control_read; int result; - const struct ads114s0x_config *config = dev->config; - struct ads114s0x_data *data = dev->data; + const struct ads1x4s0x_config *config = dev->config; + struct ads1x4s0x_data *data = dev->data; adc_context_init(&data->ctx); k_sem_init(&data->data_ready_signal, 0, 1); k_sem_init(&data->acquire_signal, 0, 1); -#ifdef CONFIG_ADC_ADS114S0X_GPIO +#ifdef CONFIG_ADC_ADS1X4S0X_GPIO k_mutex_init(&data->gpio_lock); -#endif /* CONFIG_ADC_ADS114S0X_GPIO */ +#endif /* CONFIG_ADC_ADS1X4S0X_GPIO */ if (!spi_is_ready_dt(&config->bus)) { LOG_ERR("%s: SPI device is not ready", dev->name); @@ -1385,7 +1385,7 @@ static int ads114s0x_init(const struct device *dev) return -EIO; } - gpio_init_callback(&data->callback_data_ready, ads114s0x_data_ready_handler, + gpio_init_callback(&data->callback_data_ready, ads1x4s0x_data_ready_handler, BIT(config->gpio_data_ready.pin)); result = gpio_add_callback(config->gpio_data_ready.port, &data->callback_data_ready); if (result != 0) { @@ -1395,34 +1395,34 @@ static int ads114s0x_init(const struct device *dev) #if CONFIG_ADC_ASYNC k_tid_t tid = k_thread_create(&data->thread, config->stack, - CONFIG_ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE, - ads114s0x_acquisition_thread, (void *)dev, NULL, NULL, - CONFIG_ADC_ADS114S0X_ASYNC_THREAD_INIT_PRIO, 0, K_NO_WAIT); - k_thread_name_set(tid, "adc_ads114s0x"); + CONFIG_ADC_ADS1X4S0X_ACQUISITION_THREAD_STACK_SIZE, + ads1x4s0x_acquisition_thread, (void *)dev, NULL, NULL, + CONFIG_ADC_ADS1X4S0X_ASYNC_THREAD_INIT_PRIO, 0, K_NO_WAIT); + k_thread_name_set(tid, "adc_ads1x4s0x"); #endif - k_busy_wait(ADS114S0X_POWER_ON_RESET_TIME_IN_US); + k_busy_wait(ADS1X4S0X_POWER_ON_RESET_TIME_IN_US); if (config->gpio_reset.port == NULL) { - result = ads114s0x_send_command(dev, ADS114S0X_COMMAND_RESET); + result = ads1x4s0x_send_command(dev, ADS1X4S0X_COMMAND_RESET); if (result != 0) { LOG_ERR("%s: unable to send RESET command", dev->name); return result; } } else { - k_busy_wait(ADS114S0X_RESET_LOW_TIME_IN_US); + k_busy_wait(ADS1X4S0X_RESET_LOW_TIME_IN_US); gpio_pin_set_dt(&config->gpio_reset, 0); } - k_busy_wait(ADS114S0X_RESET_DELAY_TIME_IN_US); + k_busy_wait(ADS1X4S0X_RESET_DELAY_TIME_IN_US); - result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_STATUS, &status); + result = ads1x4s0x_read_register(dev, ADS1X4S0X_REGISTER_STATUS, &status); if (result != 0) { LOG_ERR("%s: unable to read status register", dev->name); return result; } - if (ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(status) == 0x01) { + if (ADS1X4S0X_REGISTER_STATUS_NOT_RDY_GET(status) == 0x01) { LOG_ERR("%s: ADS114 is not yet ready", dev->name); return -EBUSY; } @@ -1431,9 +1431,9 @@ static int ads114s0x_init(const struct device *dev) * Activate internal voltage reference during initialization to * avoid the necessary setup time for it to settle later on. */ - ADS114S0X_REGISTER_REF_SET_DEFAULTS(reference_control); + ADS1X4S0X_REGISTER_REF_SET_DEFAULTS(reference_control); - result = ads114s0x_write_register(dev, ADS114S0X_REGISTER_REF, reference_control); + result = ads1x4s0x_write_register(dev, ADS1X4S0X_REGISTER_REF, reference_control); if (result != 0) { LOG_ERR("%s: unable to set default reference control values", dev->name); return result; @@ -1442,7 +1442,7 @@ static int ads114s0x_init(const struct device *dev) /* * Ensure that the internal voltage reference is active. */ - result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_REF, &reference_control_read); + result = ads1x4s0x_read_register(dev, ADS1X4S0X_REGISTER_REF, &reference_control_read); if (result != 0) { LOG_ERR("%s: unable to read reference control values", dev->name); return result; @@ -1454,12 +1454,12 @@ static int ads114s0x_init(const struct device *dev) return -EIO; } -#ifdef CONFIG_ADC_ADS114S0X_GPIO +#ifdef CONFIG_ADC_ADS1X4S0X_GPIO data->gpio_enabled = 0x00; data->gpio_direction = 0x0F; data->gpio_value = 0x00; - result = ads114s0x_gpio_write_config(dev); + result = ads1x4s0x_gpio_write_config(dev); if (result != 0) { LOG_ERR("%s: unable to configure defaults for GPIOs", dev->name); @@ -1473,11 +1473,11 @@ static int ads114s0x_init(const struct device *dev) } static DEVICE_API(adc, api) = { - .channel_setup = ads114s0x_channel_setup, - .read = ads114s0x_read, - .ref_internal = ADS114S0X_REF_INTERNAL, + .channel_setup = ads1x4s0x_channel_setup, + .read = ads1x4s0x_read, + .ref_internal = ADS1X4S0X_REF_INTERNAL, #ifdef CONFIG_ADC_ASYNC - .read_async = ads114s0x_adc_read_async, + .read_async = ads1x4s0x_adc_read_async, #endif }; @@ -1486,12 +1486,12 @@ BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY, #define DT_DRV_COMPAT ti_ads114s08 -#define ADC_ADS114S0X_INST_DEFINE(n) \ +#define ADC_ADS1X4S0X_INST_DEFINE(n) \ IF_ENABLED( \ CONFIG_ADC_ASYNC, \ (static K_KERNEL_STACK_DEFINE( \ - thread_stack_##n, CONFIG_ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE);)) \ - static const struct ads114s0x_config config_##n = { \ + thread_stack_##n, CONFIG_ADC_ADS1X4S0X_ACQUISITION_THREAD_STACK_SIZE);)) \ + static const struct ads1x4s0x_config config_##n = { \ .bus = SPI_DT_SPEC_INST_GET( \ n, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \ IF_ENABLED(CONFIG_ADC_ASYNC, (.stack = thread_stack_##n,)) \ @@ -1501,8 +1501,8 @@ BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY, .idac_current = DT_INST_PROP(n, idac_current), \ .vbias_level = DT_INST_PROP(n, vbias_level), \ }; \ - static struct ads114s0x_data data_##n; \ - DEVICE_DT_INST_DEFINE(n, ads114s0x_init, NULL, &data_##n, &config_##n, POST_KERNEL, \ + static struct ads1x4s0x_data data_##n; \ + DEVICE_DT_INST_DEFINE(n, ads1x4s0x_init, NULL, &data_##n, &config_##n, POST_KERNEL, \ CONFIG_ADC_INIT_PRIORITY, &api); -DT_INST_FOREACH_STATUS_OKAY(ADC_ADS114S0X_INST_DEFINE); +DT_INST_FOREACH_STATUS_OKAY(ADC_ADS1X4S0X_INST_DEFINE); diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 1cfc120ff28..d55132dcba1 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -7,7 +7,7 @@ zephyr_library() # zephyr-keep-sorted-start zephyr_library_sources_ifdef(CONFIG_GPIO_AD559X gpio_ad559x.c) zephyr_library_sources_ifdef(CONFIG_GPIO_ADP5585 gpio_adp5585.c) -zephyr_library_sources_ifdef(CONFIG_GPIO_ADS114S0X gpio_ads114s0x.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_ADS1X4S0X gpio_ads114s0x.c) zephyr_library_sources_ifdef(CONFIG_GPIO_ALTERA_PIO gpio_altera_pio.c) zephyr_library_sources_ifdef(CONFIG_GPIO_AMBIQ gpio_ambiq.c) zephyr_library_sources_ifdef(CONFIG_GPIO_ANDES_ATCGPIO100 gpio_andes_atcgpio100.c) diff --git a/drivers/gpio/Kconfig.ads114s0x b/drivers/gpio/Kconfig.ads114s0x index 1dd642c6def..39fca26923e 100644 --- a/drivers/gpio/Kconfig.ads114s0x +++ b/drivers/gpio/Kconfig.ads114s0x @@ -1,25 +1,25 @@ -# ADS114S0x GPIO configuration options +# ADS1X4S0X GPIO configuration options # Copyright (c) 2023 SILA Embedded Solutions GmbH # SPDX-License-Identifier: Apache-2.0 -menuconfig GPIO_ADS114S0X - bool "ADS114S0x GPIO driver" +menuconfig GPIO_ADS1X4S0X + bool "ADS1X4S0X GPIO driver" default y - depends on DT_HAS_TI_ADS114S0X_GPIO_ENABLED - depends on ADC_ADS114S0X_GPIO + depends on DT_HAS_TI_ADS1X4S0X_GPIO_ENABLED + depends on ADC_ADS1X4S0X_GPIO help - Enable GPIO driver for ADS114S0x. + Enable GPIO driver for ADS1X4S0X. - The ADS114S0x is a multi-channel analog frontend (AFE). + The ADS1X4S0X is a multi-channel analog frontend (AFE). - The GPIO port of the ADS114S0x (GPIO0 to GPIO3) is exposed as a + The GPIO port of the ADS1X4S0X (GPIO0 to GPIO3) is exposed as a GPIO controller driver with read/write support. -config GPIO_ADS114S0X_INIT_PRIORITY +config GPIO_ADS1X4S0X_INIT_PRIORITY int "Driver init priority" default 99 - depends on GPIO_ADS114S0X + depends on GPIO_ADS1X4S0X help Device driver initialization priority. This driver must be - initialized after the ADS114S0x ADC driver. + initialized after the ADS1X4S0X ADC driver. diff --git a/drivers/gpio/gpio_ads114s0x.c b/drivers/gpio/gpio_ads114s0x.c index 5ccbc4b553e..07aca4f4597 100644 --- a/drivers/gpio/gpio_ads114s0x.c +++ b/drivers/gpio/gpio_ads114s0x.c @@ -9,37 +9,37 @@ * @brief GPIO driver for the ADS114S0x AFE. */ -#define DT_DRV_COMPAT ti_ads114s0x_gpio +#define DT_DRV_COMPAT ti_ads1x4s0x_gpio #include #include #define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL #include -LOG_MODULE_REGISTER(gpio_ads114s0x); +LOG_MODULE_REGISTER(gpio_ads1x4s0x); #include #include -struct gpio_ads114s0x_config { +struct gpio_ads1x4s0x_config { /* gpio_driver_config needs to be first */ struct gpio_driver_config common; const struct device *parent; }; -struct gpio_ads114s0x_data { +struct gpio_ads1x4s0x_data { /* gpio_driver_data needs to be first */ struct gpio_driver_data common; }; -static int gpio_ads114s0x_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +static int gpio_ads1x4s0x_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) { - const struct gpio_ads114s0x_config *config = dev->config; + const struct gpio_ads1x4s0x_config *config = dev->config; int err = 0; if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) { - return ads114s0x_gpio_deconfigure(config->parent, pin); + return ads1x4s0x_gpio_deconfigure(config->parent, pin); } if ((flags & GPIO_SINGLE_ENDED) != 0) { @@ -51,16 +51,16 @@ static int gpio_ads114s0x_config(const struct device *dev, gpio_pin_t pin, gpio_ } if (flags & GPIO_INT_ENABLE) { - /* ads114s0x GPIOs do not support interrupts */ + /* ads1x4s0x GPIOs do not support interrupts */ return -ENOTSUP; } switch (flags & GPIO_DIR_MASK) { case GPIO_INPUT: - err = ads114s0x_gpio_set_input(config->parent, pin); + err = ads1x4s0x_gpio_set_input(config->parent, pin); break; case GPIO_OUTPUT: - err = ads114s0x_gpio_set_output(config->parent, pin, + err = ads1x4s0x_gpio_set_output(config->parent, pin, (flags & GPIO_OUTPUT_INIT_HIGH) != 0); break; default: @@ -70,76 +70,76 @@ static int gpio_ads114s0x_config(const struct device *dev, gpio_pin_t pin, gpio_ return err; } -static int gpio_ads114s0x_port_get_raw(const struct device *dev, gpio_port_value_t *value) +static int gpio_ads1x4s0x_port_get_raw(const struct device *dev, gpio_port_value_t *value) { - const struct gpio_ads114s0x_config *config = dev->config; + const struct gpio_ads1x4s0x_config *config = dev->config; - return ads114s0x_gpio_port_get_raw(config->parent, value); + return ads1x4s0x_gpio_port_get_raw(config->parent, value); } -static int gpio_ads114s0x_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, +static int gpio_ads1x4s0x_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, gpio_port_value_t value) { - const struct gpio_ads114s0x_config *config = dev->config; + const struct gpio_ads1x4s0x_config *config = dev->config; - return ads114s0x_gpio_port_set_masked_raw(config->parent, mask, value); + return ads1x4s0x_gpio_port_set_masked_raw(config->parent, mask, value); } -static int gpio_ads114s0x_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +static int gpio_ads1x4s0x_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) { - const struct gpio_ads114s0x_config *config = dev->config; + const struct gpio_ads1x4s0x_config *config = dev->config; - return ads114s0x_gpio_port_set_masked_raw(config->parent, pins, pins); + return ads1x4s0x_gpio_port_set_masked_raw(config->parent, pins, pins); } -static int gpio_ads114s0x_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +static int gpio_ads1x4s0x_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) { - const struct gpio_ads114s0x_config *config = dev->config; + const struct gpio_ads1x4s0x_config *config = dev->config; - return ads114s0x_gpio_port_set_masked_raw(config->parent, pins, 0); + return ads1x4s0x_gpio_port_set_masked_raw(config->parent, pins, 0); } -static int gpio_ads114s0x_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +static int gpio_ads1x4s0x_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) { - const struct gpio_ads114s0x_config *config = dev->config; + const struct gpio_ads1x4s0x_config *config = dev->config; - return ads114s0x_gpio_port_toggle_bits(config->parent, pins); + return ads1x4s0x_gpio_port_toggle_bits(config->parent, pins); } -static int gpio_ads114s0x_init(const struct device *dev) +static int gpio_ads1x4s0x_init(const struct device *dev) { - const struct gpio_ads114s0x_config *config = dev->config; + const struct gpio_ads1x4s0x_config *config = dev->config; if (!device_is_ready(config->parent)) { - LOG_ERR("parent ads114s0x device '%s' not ready", config->parent->name); + LOG_ERR("parent ads1x4s0x device '%s' not ready", config->parent->name); return -EINVAL; } return 0; } -static DEVICE_API(gpio, gpio_ads114s0x_api) = { - .pin_configure = gpio_ads114s0x_config, - .port_set_masked_raw = gpio_ads114s0x_port_set_masked_raw, - .port_set_bits_raw = gpio_ads114s0x_port_set_bits_raw, - .port_clear_bits_raw = gpio_ads114s0x_port_clear_bits_raw, - .port_toggle_bits = gpio_ads114s0x_port_toggle_bits, - .port_get_raw = gpio_ads114s0x_port_get_raw, +static DEVICE_API(gpio, gpio_ads1x4s0x_api) = { + .pin_configure = gpio_ads1x4s0x_config, + .port_set_masked_raw = gpio_ads1x4s0x_port_set_masked_raw, + .port_set_bits_raw = gpio_ads1x4s0x_port_set_bits_raw, + .port_clear_bits_raw = gpio_ads1x4s0x_port_clear_bits_raw, + .port_toggle_bits = gpio_ads1x4s0x_port_toggle_bits, + .port_get_raw = gpio_ads1x4s0x_port_get_raw, }; -BUILD_ASSERT(CONFIG_GPIO_ADS114S0X_INIT_PRIORITY > CONFIG_ADC_INIT_PRIORITY, - "ADS114S0X GPIO driver must be initialized after ADS114S0X ADC driver"); +BUILD_ASSERT(CONFIG_GPIO_ADS1X4S0X_INIT_PRIORITY > CONFIG_ADC_INIT_PRIORITY, + "ADS1X4S0X GPIO driver must be initialized after ADS1X4S0X ADC driver"); -#define GPIO_ADS114S0X_DEVICE(id) \ - static const struct gpio_ads114s0x_config gpio_ads114s0x_##id##_cfg = { \ +#define GPIO_ADS1X4S0X_DEVICE(id) \ + static const struct gpio_ads1x4s0x_config gpio_ads1x4s0x_##id##_cfg = { \ .common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id)}, \ .parent = DEVICE_DT_GET(DT_INST_BUS(id)), \ }; \ \ - static struct gpio_ads114s0x_data gpio_ads114s0x_##id##_data; \ + static struct gpio_ads1x4s0x_data gpio_ads1x4s0x_##id##_data; \ \ - DEVICE_DT_INST_DEFINE(id, gpio_ads114s0x_init, NULL, &gpio_ads114s0x_##id##_data, \ - &gpio_ads114s0x_##id##_cfg, POST_KERNEL, \ - CONFIG_GPIO_ADS114S0X_INIT_PRIORITY, &gpio_ads114s0x_api); + DEVICE_DT_INST_DEFINE(id, gpio_ads1x4s0x_init, NULL, &gpio_ads1x4s0x_##id##_data, \ + &gpio_ads1x4s0x_##id##_cfg, POST_KERNEL, \ + CONFIG_GPIO_ADS1X4S0X_INIT_PRIORITY, &gpio_ads1x4s0x_api); -DT_INST_FOREACH_STATUS_OKAY(GPIO_ADS114S0X_DEVICE) +DT_INST_FOREACH_STATUS_OKAY(GPIO_ADS1X4S0X_DEVICE) diff --git a/dts/bindings/gpio/ti,ads114s0x-gpio.yaml b/dts/bindings/gpio/ti,ads114s0x-gpio.yaml index 62a7a483aa1..4c3604e20ff 100644 --- a/dts/bindings/gpio/ti,ads114s0x-gpio.yaml +++ b/dts/bindings/gpio/ti,ads114s0x-gpio.yaml @@ -6,7 +6,7 @@ description: TI ADS114S0x GPIO controller binding -compatible: "ti,ads114s0x-gpio" +compatible: "ti,ads1x4s0x-gpio" include: [gpio-controller.yaml, base.yaml] diff --git a/include/zephyr/drivers/adc/ads114s0x.h b/include/zephyr/drivers/adc/ads114s0x.h index af8cae7a96a..2f4c7a14829 100644 --- a/include/zephyr/drivers/adc/ads114s0x.h +++ b/include/zephyr/drivers/adc/ads114s0x.h @@ -4,32 +4,32 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DRIVERS_ADC_ADS114S0X_H_ -#define ZEPHYR_INCLUDE_DRIVERS_ADC_ADS114S0X_H_ +#ifndef ZEPHYR_INCLUDE_DRIVERS_ADC_ADS1X4S0X_H_ +#define ZEPHYR_INCLUDE_DRIVERS_ADC_ADS1X4S0X_H_ #include #include -int ads114s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value); +int ads1x4s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value); -int ads114s0x_gpio_set_input(const struct device *dev, uint8_t pin); +int ads1x4s0x_gpio_set_input(const struct device *dev, uint8_t pin); -int ads114s0x_gpio_deconfigure(const struct device *dev, uint8_t pin); +int ads1x4s0x_gpio_deconfigure(const struct device *dev, uint8_t pin); -int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, +int ads1x4s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool value); -int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, +int ads1x4s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *value); -int ads114s0x_gpio_port_get_raw(const struct device *dev, +int ads1x4s0x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value); -int ads114s0x_gpio_port_set_masked_raw(const struct device *dev, +int ads1x4s0x_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, gpio_port_value_t value); -int ads114s0x_gpio_port_toggle_bits(const struct device *dev, +int ads1x4s0x_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins); -#endif /* ZEPHYR_INCLUDE_DRIVERS_ADC_ADS114S0X_H_ */ +#endif /* ZEPHYR_INCLUDE_DRIVERS_ADC_ADS1X4S0X_H_ */ diff --git a/include/zephyr/dt-bindings/adc/ads114s0x_adc.h b/include/zephyr/dt-bindings/adc/ads114s0x_adc.h index c54b1c4c07b..51367aa0447 100644 --- a/include/zephyr/dt-bindings/adc/ads114s0x_adc.h +++ b/include/zephyr/dt-bindings/adc/ads114s0x_adc.h @@ -4,26 +4,26 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS114S0X_ADC_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS114S0X_ADC_H_ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS1X4S0X_ADC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS1X4S0X_ADC_H_ /* * These are the available data rates described as samples per second. They * can be used with the time unit ticks for the acquisition time. */ -#define ADS114S0X_CONFIG_DR_2_5 0 -#define ADS114S0X_CONFIG_DR_5 1 -#define ADS114S0X_CONFIG_DR_10 2 -#define ADS114S0X_CONFIG_DR_16_6 3 -#define ADS114S0X_CONFIG_DR_20 4 -#define ADS114S0X_CONFIG_DR_50 5 -#define ADS114S0X_CONFIG_DR_60 6 -#define ADS114S0X_CONFIG_DR_100 7 -#define ADS114S0X_CONFIG_DR_200 8 -#define ADS114S0X_CONFIG_DR_400 9 -#define ADS114S0X_CONFIG_DR_800 10 -#define ADS114S0X_CONFIG_DR_1000 11 -#define ADS114S0X_CONFIG_DR_2000 12 -#define ADS114S0X_CONFIG_DR_4000 13 +#define ADS1X4S0X_CONFIG_DR_2_5 0 +#define ADS1X4S0X_CONFIG_DR_5 1 +#define ADS1X4S0X_CONFIG_DR_10 2 +#define ADS1X4S0X_CONFIG_DR_16_6 3 +#define ADS1X4S0X_CONFIG_DR_20 4 +#define ADS1X4S0X_CONFIG_DR_50 5 +#define ADS1X4S0X_CONFIG_DR_60 6 +#define ADS1X4S0X_CONFIG_DR_100 7 +#define ADS1X4S0X_CONFIG_DR_200 8 +#define ADS1X4S0X_CONFIG_DR_400 9 +#define ADS1X4S0X_CONFIG_DR_800 10 +#define ADS1X4S0X_CONFIG_DR_1000 11 +#define ADS1X4S0X_CONFIG_DR_2000 12 +#define ADS1X4S0X_CONFIG_DR_4000 13 -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS114S0X_ADC_H_ */ +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS1X4S0X_ADC_H_ */ diff --git a/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.overlay b/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.overlay index d93e6b1e233..b3594208123 100644 --- a/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.overlay +++ b/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.overlay @@ -40,7 +40,7 @@ start-sync-gpios = <&test_gpio 0 0>; test_spi_ads114s08_gpio: ads114s0x_gpio { - compatible = "ti,ads114s0x-gpio"; + compatible = "ti,ads1x4s0x-gpio"; gpio-controller; ngpios = <4>; #gpio-cells = <2>; diff --git a/tests/drivers/build_all/gpio/testcase.yaml b/tests/drivers/build_all/gpio/testcase.yaml index 99f9fead947..68ed69e3cfc 100644 --- a/tests/drivers/build_all/gpio/testcase.yaml +++ b/tests/drivers/build_all/gpio/testcase.yaml @@ -26,7 +26,7 @@ tests: depends_on: gpio extra_args: DTC_OVERLAY_FILE="altera.overlay" - drivers.gpio.build.adc_ads1145s0x_gpio: + drivers.gpio.build.adc_ads1x4s0x_gpio: min_ram: 32 platform_allow: - m5stack_core2/esp32/procpu @@ -44,7 +44,7 @@ tests: extra_configs: - CONFIG_ADC=y - CONFIG_ADC_INIT_PRIORITY=80 - - CONFIG_ADC_ADS114S0X_GPIO=y + - CONFIG_ADC_ADS1X4S0X_GPIO=y drivers.gpio.build.adc_lmp90xxx_gpio: min_ram: 32