From 41c36357bd9bcbaee6a625a2a70ad265f4e4f8ad Mon Sep 17 00:00:00 2001 From: Manuel Arguelles Date: Sun, 7 Aug 2022 04:25:54 +0700 Subject: [PATCH] soc: arm: introduce NXP S32Z/E support This patch introduces support for NXP S32 devices, specifically for S32Z27 from S32Z/E family. NXP S32Z27 processors are composed of two Real-Time Units (RTU) containing each four ARM Cortex-R52 cores with flexible split/lock configuration, and dedicated internal SRAM. Signed-off-by: Manuel Arguelles --- dts/arm/nxp/nxp_s32z27x_r52.dtsi | 96 +++++++++++++++++++ dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi | 18 ++++ dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi | 18 ++++ modules/Kconfig | 1 + modules/Kconfig.s32 | 9 ++ soc/arm/nxp_s32/CMakeLists.txt | 5 + soc/arm/nxp_s32/Kconfig | 18 ++++ soc/arm/nxp_s32/Kconfig.defconfig | 4 + soc/arm/nxp_s32/Kconfig.soc | 4 + soc/arm/nxp_s32/common/CMakeLists.txt | 4 + soc/arm/nxp_s32/common/osif.c | 26 +++++ soc/arm/nxp_s32/s32ze/CMakeLists.txt | 8 ++ .../nxp_s32/s32ze/Kconfig.defconfig.s32z27 | 9 ++ .../nxp_s32/s32ze/Kconfig.defconfig.series | 34 +++++++ soc/arm/nxp_s32/s32ze/Kconfig.series | 19 ++++ soc/arm/nxp_s32/s32ze/Kconfig.soc | 37 +++++++ soc/arm/nxp_s32/s32ze/linker.ld | 7 ++ soc/arm/nxp_s32/s32ze/mpu_regions.c | 42 ++++++++ soc/arm/nxp_s32/s32ze/soc.c | 48 ++++++++++ soc/arm/nxp_s32/s32ze/soc.h | 13 +++ west.yml | 2 +- 21 files changed, 421 insertions(+), 1 deletion(-) create mode 100644 dts/arm/nxp/nxp_s32z27x_r52.dtsi create mode 100644 dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi create mode 100644 dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi create mode 100644 modules/Kconfig.s32 create mode 100644 soc/arm/nxp_s32/CMakeLists.txt create mode 100644 soc/arm/nxp_s32/Kconfig create mode 100644 soc/arm/nxp_s32/Kconfig.defconfig create mode 100644 soc/arm/nxp_s32/Kconfig.soc create mode 100644 soc/arm/nxp_s32/common/CMakeLists.txt create mode 100644 soc/arm/nxp_s32/common/osif.c create mode 100644 soc/arm/nxp_s32/s32ze/CMakeLists.txt create mode 100644 soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 create mode 100644 soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series create mode 100644 soc/arm/nxp_s32/s32ze/Kconfig.series create mode 100644 soc/arm/nxp_s32/s32ze/Kconfig.soc create mode 100644 soc/arm/nxp_s32/s32ze/linker.ld create mode 100644 soc/arm/nxp_s32/s32ze/mpu_regions.c create mode 100644 soc/arm/nxp_s32/s32ze/soc.c create mode 100644 soc/arm/nxp_s32/s32ze/soc.h diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi new file mode 100644 index 00000000000..fda7b6893d3 --- /dev/null +++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi @@ -0,0 +1,96 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <3>; + }; + + cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <4>; + }; + + cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <5>; + }; + + cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <6>; + }; + + cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <7>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8_timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; + + soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@47800000 { + compatible = "arm,gic"; + reg = <0x47800000 0x10000>, + <0x47900000 0x80000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; + + sram0: memory@31780000 { + compatible = "mmio-sram"; + reg = <0x31780000 DT_SIZE_M(1)>; + }; + + sram1: memory@35780000 { + compatible = "mmio-sram"; + reg = <0x35780000 DT_SIZE_M(1)>; + }; + }; +}; diff --git a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi new file mode 100644 index 00000000000..7a5c3fdc099 --- /dev/null +++ b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + + cpus { + /delete-node/ cpu@4; + /delete-node/ cpu@5; + /delete-node/ cpu@6; + /delete-node/ cpu@7; + }; + +}; diff --git a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi new file mode 100644 index 00000000000..c3792989512 --- /dev/null +++ b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + + cpus { + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; + }; + +}; diff --git a/modules/Kconfig b/modules/Kconfig index f96f418c11b..0d59008726d 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -28,6 +28,7 @@ source "modules/Kconfig.mcux" source "modules/Kconfig.microchip" source "modules/Kconfig.nuvoton" source "modules/Kconfig.open-amp" +source "modules/Kconfig.s32" source "modules/Kconfig.silabs" source "modules/Kconfig.simplelink" source "modules/Kconfig.sof" diff --git a/modules/Kconfig.s32 b/modules/Kconfig.s32 new file mode 100644 index 00000000000..9d3bc2544a1 --- /dev/null +++ b/modules/Kconfig.s32 @@ -0,0 +1,9 @@ +# NXP S32 MCUs family + +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +config HAS_S32_HAL + bool + select HAS_CMSIS_CORE + depends on SOC_FAMILY_S32 diff --git a/soc/arm/nxp_s32/CMakeLists.txt b/soc/arm/nxp_s32/CMakeLists.txt new file mode 100644 index 00000000000..0e8dc13e78c --- /dev/null +++ b/soc/arm/nxp_s32/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) +add_subdirectory(common) diff --git a/soc/arm/nxp_s32/Kconfig b/soc/arm/nxp_s32/Kconfig new file mode 100644 index 00000000000..06f1d737586 --- /dev/null +++ b/soc/arm/nxp_s32/Kconfig @@ -0,0 +1,18 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_S32 + bool + +if SOC_FAMILY_S32 + +config SOC_FAMILY + string + default "nxp_s32" + +source "soc/arm/nxp_s32/*/Kconfig.soc" + +config SOC_PART_NUMBER + default SOC_PART_NUMBER_S32ZE_R52 if SOC_SERIES_S32ZE_R52 + +endif # SOC_FAMILY_S32 diff --git a/soc/arm/nxp_s32/Kconfig.defconfig b/soc/arm/nxp_s32/Kconfig.defconfig new file mode 100644 index 00000000000..49c9a142934 --- /dev/null +++ b/soc/arm/nxp_s32/Kconfig.defconfig @@ -0,0 +1,4 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +source "soc/arm/nxp_s32/*/Kconfig.defconfig.series" diff --git a/soc/arm/nxp_s32/Kconfig.soc b/soc/arm/nxp_s32/Kconfig.soc new file mode 100644 index 00000000000..85c8414b5ee --- /dev/null +++ b/soc/arm/nxp_s32/Kconfig.soc @@ -0,0 +1,4 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +source "soc/arm/nxp_s32/*/Kconfig.series" diff --git a/soc/arm/nxp_s32/common/CMakeLists.txt b/soc/arm/nxp_s32/common/CMakeLists.txt new file mode 100644 index 00000000000..bb1f238e79b --- /dev/null +++ b/soc/arm/nxp_s32/common/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(osif.c) diff --git a/soc/arm/nxp_s32/common/osif.c b/soc/arm/nxp_s32/common/osif.c new file mode 100644 index 00000000000..5bfada661b1 --- /dev/null +++ b/soc/arm/nxp_s32/common/osif.c @@ -0,0 +1,26 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#if defined(CONFIG_SOC_S32Z27_R52) +#include +#endif + +/* Required by OsIf timer initialization but not used with Zephyr, so no values configured */ +static const OsIf_ConfigType osif_config; +const OsIf_ConfigType *const OsIf_apxPredefinedConfig[OSIF_MAX_COREIDX_SUPPORTED] = { + &osif_config +}; + +/* + * OsIf call to get the processor number of the core making the access. + */ +uint8_t Sys_GetCoreID(void) +{ + return ((uint8_t)(IP_MSCM->CPXNUM & MSCM_CPXNUM_CPN_MASK)); +} diff --git a/soc/arm/nxp_s32/s32ze/CMakeLists.txt b/soc/arm/nxp_s32/s32ze/CMakeLists.txt new file mode 100644 index 00000000000..155354816f3 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources( + soc.c +) + +zephyr_library_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c) diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 new file mode 100644 index 00000000000..2a88861fc98 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 @@ -0,0 +1,9 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_S32Z27_R52 + +config SOC + default "s32z27" + +endif # SOC_S32Z27_R52 diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series new file mode 100644 index 00000000000..9edf94e08e1 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series @@ -0,0 +1,34 @@ +# NXP S32Z/E MCUs family default configuration + +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_S32ZE_R52 + +config SOC_SERIES + default "s32ze" + +config NUM_IRQS + # must be >= the highest interrupt number used + default 991 + +config FPU + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 2000000 + +config MAIN_STACK_SIZE + default 1024 + +if !XIP +config FLASH_SIZE + default 0 + +config FLASH_BASE_ADDRESS + default 0 +endif # !XIP + +source "soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32*" + +endif # SOC_SERIES_S32ZE_R52 diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.series b/soc/arm/nxp_s32/s32ze/Kconfig.series new file mode 100644 index 00000000000..cb60a3e75d7 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/Kconfig.series @@ -0,0 +1,19 @@ +# NXP S32Z/E MCUs family + +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32ZE_R52 + bool "NXP S32Z/E series" + select ARM + select ARM_ARCH_TIMER + select CPU_CORTEX_R52 + select CPU_HAS_DCLS + select CPU_HAS_ARM_MPU + select GIC_V3 + select GIC_SINGLE_SECURITY_STATE + select VFP_DP_D16 + select PLATFORM_SPECIFIC_INIT + select SOC_FAMILY_S32 + help + Enable support for NXP S32Z/E MCUs family on Cortex-R52 cores. diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.soc b/soc/arm/nxp_s32/s32ze/Kconfig.soc new file mode 100644 index 00000000000..4013db2b2b1 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/Kconfig.soc @@ -0,0 +1,37 @@ +# NXP S32Z/E MCUs family + +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "NXP S32Z/E MCUs family SoC selection" + depends on SOC_SERIES_S32ZE_R52 + +config SOC_S32Z27_R52 + bool "SOC_S32Z27_R52" + select HAS_S32_HAL + +endchoice + +if SOC_SERIES_S32ZE_R52 + +config SOC_PART_NUMBER_S32Z27 + bool + +config SOC_PART_NUMBER_S32ZE_R52 + string + default "S32Z27" if SOC_PART_NUMBER_S32Z27 + help + This string holds the full part number of the SoC. It is a hidden option + that you should not set directly. The part number selection choice defines + the default value for this string. + +config INIT_CLOCK_AT_BOOT_TIME + bool "Initialize clocks at boot time" + default y + help + Initialize clocks at boot time with the configuration generated through the + driver's configurator, instead of using the default SoC clock configuration + at reset. + +endif # SOC_SERIES_S32ZE_R52 diff --git a/soc/arm/nxp_s32/s32ze/linker.ld b/soc/arm/nxp_s32/s32ze/linker.ld new file mode 100644 index 00000000000..c8a7570e891 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/linker.ld @@ -0,0 +1,7 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/nxp_s32/s32ze/mpu_regions.c b/soc/arm/nxp_s32/s32ze/mpu_regions.c new file mode 100644 index 00000000000..bfbd0f85785 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/mpu_regions.c @@ -0,0 +1,42 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define DEVICE_REGION_START 0x40000000UL +#define DEVICE_REGION_END 0x76FFFFFFUL + +static const struct arm_mpu_region mpu_regions[] = { + MPU_REGION_ENTRY("vector", + (uintptr_t)_vector_start, + REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)), + + MPU_REGION_ENTRY("SRAM_TEXT", + (uintptr_t)__text_region_start, + REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)), + + MPU_REGION_ENTRY("SRAM_RODATA", + (uintptr_t)__rodata_region_start, + REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)), + + MPU_REGION_ENTRY("SRAM_DATA", +#ifdef CONFIG_USERSPACE + (uintptr_t)_app_smem_start, +#else + (uintptr_t)__kernel_ram_start, +#endif + REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)), + + MPU_REGION_ENTRY("DEVICE", + DEVICE_REGION_START, + REGION_DEVICE_ATTR(DEVICE_REGION_END)), +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/soc/arm/nxp_s32/s32ze/soc.c b/soc/arm/nxp_s32/s32ze/soc.c new file mode 100644 index 00000000000..cc83dc42163 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/soc.c @@ -0,0 +1,48 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_INIT_CLOCK_AT_BOOT_TIME +#include +#include +#endif + +void z_arm_platform_init(void) +{ + /* enable peripheral port access at EL1 and EL0 */ + __asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n"); + __asm__ volatile("orr r0, #1\n"); + __asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n"); + __DSB(); + __ISB(); +} + +static int soc_init(const struct device *arg) +{ + ARG_UNUSED(arg); + + /* Install default handler that simply resets the CPU if configured in the + * kernel, NOP otherwise + */ + NMI_INIT(); + + OsIf_Init(NULL); + +#ifdef CONFIG_INIT_CLOCK_AT_BOOT_TIME + /* Initialize clocks with tool generated code */ + Clock_Ip_Init(Clock_Ip_aClockConfig); +#endif + + return 0; +} + +SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/arm/nxp_s32/s32ze/soc.h b/soc/arm/nxp_s32/s32ze/soc.h new file mode 100644 index 00000000000..1bacb430a00 --- /dev/null +++ b/soc/arm/nxp_s32/s32ze/soc.h @@ -0,0 +1,13 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _NXP_S32_S32ZE_SOC_H_ +#define _NXP_S32_S32ZE_SOC_H_ + +/* Do not let CMSIS to handle GIC */ +#define __GIC_PRESENT 0 + +#endif /* _NXP_S32_S32ZE_SOC_H_ */ diff --git a/west.yml b/west.yml index ea5e486042b..dd64150442e 100644 --- a/west.yml +++ b/west.yml @@ -88,7 +88,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 708c95825b0d5279620935a1356299fff5dfbc6e + revision: 3e3648526824cc5b52ab59d5dd308473e291b760 path: modules/hal/nxp groups: - hal