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board: nrf: Add nRF54LM20DK board

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Adding board for nRF54LM20A device.

Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
This commit is contained in:
Karol Lasończyk 2025-06-23 16:27:22 +02:00 committed by Daniel DeGrasse
parent 387520c867
commit 3d1fa8b333
14 changed files with 732 additions and 0 deletions
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boards/nordic/nrf54lm20dk/Kconfig.defconfig Normal file
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# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP
config ROM_START_OFFSET
default 0x800 if BOOTLOADER_MCUBOOT
endif # BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP

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boards/nordic/nrf54lm20dk/Kconfig.nrf54lm20dk Normal file
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# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config BOARD_NRF54LM20DK
select SOC_NRF54LM20A_ENGA_CPUAPP if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP
select SOC_NRF54LM20A_ENGA_CPUFLPR if BOARD_NRF54LM20DK_NRF54LM20A_CPUFLPR

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boards/nordic/nrf54lm20dk/board.cmake Normal file
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# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP)
board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
elseif(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR)
board_runner_args(jlink "--speed=4000")
endif()
include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

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boards/nordic/nrf54lm20dk/board.yml Normal file
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board:
name: nrf54lm20dk
full_name: nRF54LM20 DK
vendor: nordic
socs:
- name: nrf54lm20a
variants:
- name: xip
cpucluster: cpuflpr
runners:
run_once:
'--recover':
- runners:
- nrfjprog
- nrfutil
run: first
groups:
- boards:
- nrf54lm20dk/nrf54lm20a/cpuapp
- nrf54lm20dk/nrf54lm20a/cpuflpr
- nrf54lm20dk/nrf54lm20a/cpuflpr/xip
'--erase':
- runners:
- nrfjprog
- jlink
- nrfutil
run: first
groups:
- boards:
- nrf54lm20dk/nrf54lm20a/cpuapp
- nrf54lm20dk/nrf54lm20a/cpuflpr
- nrf54lm20dk/nrf54lm20a/cpuflpr/xip
'--reset':
- runners:
- nrfjprog
- jlink
- nrfutil
run: last
groups:
- boards:
- nrf54lm20dk/nrf54lm20a/cpuapp
- nrf54lm20dk/nrf54lm20a/cpuflpr
- nrf54lm20dk/nrf54lm20a/cpuflpr/xip

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boards/nordic/nrf54lm20dk/doc/index.rst Normal file
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.. zephyr:board:: nrf54lm20dk
Overview
********
The nRF54LM20 Development Kit hardware provides support for the Nordic Semiconductor
nRF54LM20A Arm Cortex-M33 CPU and the following devices:
* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
* CLOCK
* RRAM
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
* MEMCONF
* :abbr:`MPU (Memory Protection Unit)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`PWM (Pulse Width Modulation)`
* :abbr:`GRTC (Global real-time counter)`
* Segger RTT (RTT Console)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
* :abbr:`WDT (Watchdog Timer)`
Hardware
********
nRF54LM20 DK has two crystal oscillators:
* High-frequency 32 MHz crystal oscillator (HFXO)
* Low-frequency 32.768 kHz crystal oscillator (LFXO)
The crystal oscillators can be configured to use either
internal or external capacitors.
Supported Features
==================
.. zephyr:board-supported-hw::
Programming and Debugging
*************************
.. zephyr:board-supported-runners::
Applications for the ``nrf54lm20dk/nrf54lm20a/cpuapp`` board target can be
built, flashed, and debugged in the usual way. See
:ref:`build_an_application` and :ref:`application_run` for more details on
building and running.
Applications for the ``nrf54lm20dk/nrf54lm20a/cpuflpr`` board target need
to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
Enter the following command to compile ``hello_world`` for the FLPR core:
.. code-block:: console
west build -p -b nrf54lm20dk/nrf54lm20a/cpuflpr --sysbuild
Flashing
========
As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
application.
.. warning::
When programming the device, you might get an error similar to the following message::
ERROR: The operation attempted is unavailable due to readback protection in
ERROR: your device. Please use --recover to unlock the device.
This error occurs when readback protection is enabled.
To disable the readback protection, you must *recover* your device.
Enter the following command to recover the core::
west flash --recover
The ``--recover`` command erases the flash memory and then writes a small binary into
the recovered flash memory.
This binary prevents the readback protection from enabling itself again after a pin
reset or power cycle.
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`.
To build and program the sample to the nRF54LM20 DK, complete the following steps:
First, connect the nRF54LM20 DK to you computer using the IMCU USB port on the DK.
Next, build the sample by running the following command:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf54lm20dk/nrf54lm20a/cpuapp
:goals: build flash
Testing the LEDs and buttons in the nRF54LM20 DK
************************************************
Test the nRF54LM20 DK with a :zephyr:code-sample:`blinky` sample.

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boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi Normal file
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/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* This file is common to the secure and non-secure domain */
#include <nordic/nrf54lm20a_enga_cpuapp.dtsi>
#include "nrf54lm20dk_nrf54lm20a-common.dtsi"
/ {
chosen {
zephyr,console = &uart20;
zephyr,shell-uart = &uart20;
zephyr,uart-mcumgr = &uart20;
zephyr,bt-mon-uart = &uart20;
zephyr,bt-c2h-uart = &uart20;
zephyr,flash-controller = &rram_controller;
zephyr,flash = &cpuapp_rram;
zephyr,bt-hci = &bt_hci_sdc;
zephyr,ieee802154 = &ieee802154;
};
};
&cpuapp_sram {
status = "okay";
};
&hfpll {
clock-frequency = <DT_FREQ_M(128)>;
};
&lfxo {
load-capacitors = "internal";
load-capacitance-femtofarad = <17000>;
};
&hfxo {
load-capacitors = "internal";
load-capacitance-femtofarad = <15000>;
};
&vregmain {
status = "okay";
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&grtc {
owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
child-owned-channels = <3 4 7 8 9 10 11>;
status = "okay";
};
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x10000 DT_SIZE_K(449)>;
};
slot0_ns_partition: partition@80400 {
label = "image-0-nonsecure";
reg = <0x80400 DT_SIZE_K(449)>;
};
slot1_partition: partition@f0800 {
label = "image-1";
reg = <0xf0800 DT_SIZE_K(449)>;
};
slot1_ns_partition: partition@160c00 {
label = "image-1-nonsecure";
reg = <0x160c00 DT_SIZE_K(449)>;
};
storage_partition: partition@1d1000 {
label = "storage";
reg = <0x1d1000 DT_SIZE_K(36)>;
};
};
};
&uart20 {
status = "okay";
};
&nfct {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpiote20 {
status = "okay";
};
&gpiote30 {
status = "okay";
};
&radio {
status = "okay";
};
&temp {
status = "okay";
};
&clock {
status = "okay";
};
&bt_hci_controller {
status = "okay";
};
&ieee802154 {
status = "okay";
};
zephyr_udc0: &usbhs {
status = "okay";
};
&spi00 {
status = "okay";
cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi00_default>;
pinctrl-1 = <&spi00_sleep>;
pinctrl-names = "default", "sleep";
mx25r64: mx25r6435f@0 {
compatible = "jedec,spi-nor";
status = "disabled";
reg = <0>;
spi-max-frequency = <8000000>;
jedec-id = [c2 28 17];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
size = <67108864>;
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <35000>;
};
};

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/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf54lm20dk_nrf54lm20a-pinctrl.dtsi"
/ {
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
label = "Green LED 1";
};
led2: led_2 {
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
label = "Green LED 2";
};
led3: led_3 {
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
label = "Green LED 3";
};
};
pwmleds {
compatible = "pwm-leds";
/*
* PWM signal can be exposed on GPIO pin only within same domain.
* There is only one domain which contains both PWM and GPIO:
* PWM20/21/22 and GPIO Port P1/P3.
* Only LEDs connected to P1/P3 can work with PWM, for example LED1.
*/
pwm_led1: pwm_led_1 {
pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio1 26 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 0";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_1>;
};
button2: button_2 {
gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_2>;
};
button3: button_3 {
gpios = <&gpio0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 3";
zephyr,code = <INPUT_KEY_3>;
};
};
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
pwm-led0 = &pwm_led1;
sw0 = &button0;
sw1 = &button1;
sw2 = &button2;
sw3 = &button3;
watchdog0 = &wdt31;
};
};
&uart20 {
current-speed = <115200>;
pinctrl-0 = <&uart20_default>;
pinctrl-1 = <&uart20_sleep>;
pinctrl-names = "default", "sleep";
};
&uart30 {
current-speed = <115200>;
pinctrl-0 = <&uart30_default>;
pinctrl-1 = <&uart30_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm20 {
status = "okay";
pinctrl-0 = <&pwm20_default>;
pinctrl-1 = <&pwm20_sleep>;
pinctrl-names = "default", "sleep";
};

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boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a-pinctrl.dtsi Normal file
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/*
* Copyright (c) 2025 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
/omit-if-no-ref/ uart20_default: uart20_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 16)>,
<NRF_PSEL(UART_RTS, 1, 18)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 17)>,
<NRF_PSEL(UART_CTS, 1, 19)>;
bias-pull-up;
};
};
/omit-if-no-ref/ uart20_sleep: uart20_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 16)>,
<NRF_PSEL(UART_RX, 1, 17)>,
<NRF_PSEL(UART_RTS, 1, 18)>,
<NRF_PSEL(UART_CTS, 1, 19)>;
low-power-enable;
};
};
/omit-if-no-ref/ pwm20_default: pwm20_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 25)>;
};
};
/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 25)>;
low-power-enable;
};
};
/omit-if-no-ref/ uart30_default: uart30_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RTS, 0, 8)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 7)>,
<NRF_PSEL(UART_CTS, 0, 9)>;
bias-pull-up;
};
};
/omit-if-no-ref/ uart30_sleep: uart30_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 7)>,
<NRF_PSEL(UART_RTS, 0, 8)>,
<NRF_PSEL(UART_CTS, 0, 9)>;
low-power-enable;
};
};
/omit-if-no-ref/ spi00_default: spi00_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
<NRF_PSEL(SPIM_MOSI, 2, 2)>,
<NRF_PSEL(SPIM_MISO, 2, 4)>;
};
};
/omit-if-no-ref/ spi00_sleep: spi00_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
<NRF_PSEL(SPIM_MOSI, 2, 2)>,
<NRF_PSEL(SPIM_MISO, 2, 4)>;
low-power-enable;
};
};
/omit-if-no-ref/ grtc_default: grtc_default {
group1 {
psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 7)>,
<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
};
};
/omit-if-no-ref/ grtc_sleep: grtc_sleep {
group1 {
psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 7)>,
<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
low-power-enable;
};
};
};

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boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts Normal file
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/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "nrf54lm20a_cpuapp_common.dtsi"
/ {
compatible = "nordic,nrf54lm20dk_nrf54lm20a-cpuapp";
model = "Nordic nRF54LM20 DK nRF54LM20A Application MCU";
chosen {
zephyr,code-partition = &slot0_partition;
zephyr,sram = &cpuapp_sram;
};
};
&bt_hci_sdc {
status = "okay";
};
&bt_hci_controller {
status = "disabled";
};
/* Get a node label for wi-fi spi to use in shield files */
wifi_spi: &spi22 {};

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boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.yaml Normal file
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# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54lm20dk/nrf54lm20a/cpuapp
name: nRF54LM20-DK-nRF54LM20A-Application
type: mcu
arch: arm
toolchain:
- gnuarmemb
- zephyr
sysbuild: true
ram: 512
flash: 449
supported:
- adc
- counter
- dmic
- gpio
- i2c
- i2s
- pwm
- spi
- watchdog

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boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_defconfig Normal file
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# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot
# be applied as the (0x0 - 0x400) is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable Cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y
# Start SYSCOUNTER on driver init
CONFIG_NRF_GRTC_START_SYSCOUNTER=y

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/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54lm20a_enga_cpuflpr.dtsi>
#include "nrf54lm20dk_nrf54lm20a-common.dtsi"
/ {
model = "Nordic nRF54LM20 DK nRF54LM20A FLPR MCU";
compatible = "nordic,nrf54lm20dk_nrf54lm20a-cpuflpr";
chosen {
zephyr,console = &uart30;
zephyr,shell-uart = &uart30;
zephyr,code-partition = &cpuflpr_code_partition;
zephyr,flash = &cpuflpr_rram;
zephyr,sram = &cpuflpr_sram;
};
};
&cpuflpr_sram {
status = "okay";
};
&cpuflpr_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: partition@0 {
label = "image-0";
reg = <0x0 DT_SIZE_K(96)>;
};
};
};
&grtc {
owned-channels = <3 4>;
status = "okay";
};
&uart30 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpiote20 {
status = "okay";
};
&gpiote30 {
status = "okay";
};

16
boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuflpr.yaml Normal file
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# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54lm20dk/nrf54lm20a/cpuflpr
name: nRF54LM20-DK-nRF54LM20A-Fast-Lightweight-Peripheral-Processor
type: mcu
arch: riscv
toolchain:
- zephyr
sysbuild: true
ram: 96
flash: 96
supported:
- counter
- gpio
- watchdog

19
boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuflpr_defconfig Normal file
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# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
CONFIG_USE_DT_CODE_PARTITION=y
# Execute from SRAM
CONFIG_XIP=n
CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL=y