diff --git a/boards/weact/stm32f446_core/Kconfig.weact_stm32f446_core b/boards/weact/stm32f446_core/Kconfig.weact_stm32f446_core new file mode 100644 index 00000000000..71f8cb118dd --- /dev/null +++ b/boards/weact/stm32f446_core/Kconfig.weact_stm32f446_core @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Siratul Islam +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WEACT_STM32F446_CORE + select SOC_STM32F446XX diff --git a/boards/weact/stm32f446_core/board.cmake b/boards/weact/stm32f446_core/board.cmake new file mode 100644 index 00000000000..4e4cb83a1fa --- /dev/null +++ b/boards/weact/stm32f446_core/board.cmake @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32F446RE" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/weact/stm32f446_core/board.yml b/boards/weact/stm32f446_core/board.yml new file mode 100644 index 00000000000..80465f65a26 --- /dev/null +++ b/boards/weact/stm32f446_core/board.yml @@ -0,0 +1,6 @@ +board: + name: weact_stm32f446_core + full_name: STM32F446 Core Board V1.1 + vendor: weact + socs: + - name: stm32f446xx diff --git a/boards/weact/stm32f446_core/doc/img/stm32f446_core.webp b/boards/weact/stm32f446_core/doc/img/stm32f446_core.webp new file mode 100644 index 00000000000..5216a0db9fa Binary files /dev/null and b/boards/weact/stm32f446_core/doc/img/stm32f446_core.webp differ diff --git a/boards/weact/stm32f446_core/doc/index.rst b/boards/weact/stm32f446_core/doc/index.rst new file mode 100644 index 00000000000..9b86e286f35 --- /dev/null +++ b/boards/weact/stm32f446_core/doc/index.rst @@ -0,0 +1,165 @@ +.. zephyr:board:: weact_stm32f446_core + +Overview +******** + +The WeAct STM32F446 Core Board is an extremely low cost and bare-bones +development board featuring the STM32F446RE, see `STM32F446RE website`_. +This is the 64-pin variant of the STM32F446x series, +see `STM32F446x reference manual`_. More info about the board available +on `WeAct Github`_. + +Hardware +******** + +The STM32F446RE based Core Board provides the following +hardware components: + +- STM32F446RE in QFPN64 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time + accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory +- 180 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 Kbytes of SRAM +- GPIO with external interrupt capability +- 3x12-bit, 2.4 MSPS ADC up to 16 channels +- 2x12-bit D/A converters +- 16-stream DMA controller +- Up to 17 Timers (twelve 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (4) +- I2C (4) +- SPI/I2S (4) +- CAN (2) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- SAI (Serial Audio Interface) +- SPDIFRX interface +- HDMI-CEC +- CRC calculation unit +- 96-bit unique ID +- RTC with hardware calendar + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (also available on USB-C for console) +- UART_2 TX/RX : PA2/PA3 +- I2C1 SCL/SDA : PB6/PB7 +- I2C2 SCL/SDA : PB10/PB11 +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 +- CAN1 TX/RX : PB9/PB8 +- SDMMC1 D0/D1/D2/D3/CLK/CMD : PC8/PC9/PC10/PC11/PC12/PD2 +- USER_PB : PC13 (Active Low) +- USER_LED : PB2 (Active High) +- USB_DM/USB_DP : PA11/PA12 + +OnBoard Features + +- USB Type-C connector +- User LED (PB2) - Active High +- User Key (PC13) - Active Low +- BOOT0 Key for DFU mode +- RESET Key +- 8MHz HSE crystal oscillator +- 32.768kHz LSE crystal oscillator +- MicroSD card slot (SDIO interface) +- SWD debug header (3.3V, GND, SWCLK, SWDIO) +- 30×2 pin headers exposing GPIO pins + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 8 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 180MHz, which is the maximum possible frequency +for the STM32F446RE. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: weact_stm32f446_core + :goals: build flash + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: weact_stm32f446_core + :goals: build flash + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/fs/fs_sample + :board: weact_stm32f446_core + :goals: build flash + + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _board release notes: + https://github.com/WeActStudio/WeActStudio.STM32F4_64Pin_CoreBoard/blob/master/README.md + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.STM32F4_64Pin_CoreBoard + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F446RE website: + https://www.st.com/en/microcontrollers-microprocessors/stm32f446re.html + +.. _STM32F446x reference manual: + https://www.st.com/resource/en/reference_manual/rm0390-stm32f446xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/weact/stm32f446_core/support/openocd.cfg b/boards/weact/stm32f446_core/support/openocd.cfg new file mode 100644 index 00000000000..451853a38bd --- /dev/null +++ b/boards/weact/stm32f446_core/support/openocd.cfg @@ -0,0 +1,18 @@ +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f4x.cfg] + +reset_config srst_only + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/weact/stm32f446_core/weact_stm32f446_core.dts b/boards/weact/stm32f446_core/weact_stm32f446_core.dts new file mode 100644 index 00000000000..83e05ed0f33 --- /dev/null +++ b/boards/weact/stm32f446_core/weact_stm32f446_core.dts @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2024 Siratul Islam + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "WeAct Studio STM32F446 Core Board"; + compatible = "weact,stm32f446-core", "st,stm32f446"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + led: led { + gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "User"; + gpios = <&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led; + sw0 = &user_button; + watchdog0 = &iwdg; + sdhc0 = &sdmmc1; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <8>; + mul-n = <360>; + div-p = <2>; + div-q = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <4>; + apb2-prescaler = <2>; +}; + + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_rx_pb8 &can1_tx_pb9>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdmmc1 { + status = "okay"; + pinctrl-0 = <&sdio_d0_pc8 &sdio_d1_pc9 + &sdio_d2_pc10 &sdio_d3_pc11 + &sdio_ck_pc12 &sdio_cmd_pd2>; + pinctrl-names = "default"; + cd-gpios = <&gpioa 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + disk-name = "SD"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; diff --git a/boards/weact/stm32f446_core/weact_stm32f446_core.yaml b/boards/weact/stm32f446_core/weact_stm32f446_core.yaml new file mode 100644 index 00000000000..b79008a3f7d --- /dev/null +++ b/boards/weact/stm32f446_core/weact_stm32f446_core.yaml @@ -0,0 +1,19 @@ +identifier: weact_stm32f446_core +name: WeAct Studio STM32F446 Core Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 128 +flash: 512 +supported: + - counter + - spi + - i2c + - uart + - can + - gpio + - watchdog + - backup_sram +vendor: weact diff --git a/boards/weact/stm32f446_core/weact_stm32f446_core_defconfig b/boards/weact/stm32f446_core/weact_stm32f446_core_defconfig new file mode 100644 index 00000000000..ecb4e20a166 --- /dev/null +++ b/boards/weact/stm32f446_core/weact_stm32f446_core_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y