From 2bef8051b2fc6613efb2cd6e4103e07f3cbeff8a Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 16 Aug 2022 15:53:04 -0500 Subject: [PATCH] soc: RT595: Add USB support 1. Update soc.c file to add USB clock setup 2. Add a linker file to move USB transfer buffer and controller buffers to USB RAM 3. Update Kconfig's to add USB support 4. Add zephyr_udc0 nodelabel Signed-off-by: Mahesh Mahadevan --- boards/arm/mimxrt595_evk/doc/index.rst | 2 + .../arm/mimxrt595_evk/mimxrt595_evk_cm33.dts | 4 + .../arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml | 1 + soc/arm/nxp_imx/rt5xx/CMakeLists.txt | 3 + .../rt5xx/Kconfig.defconfig.mimxrt595_cm33 | 8 ++ soc/arm/nxp_imx/rt5xx/Kconfig.soc | 3 + soc/arm/nxp_imx/rt5xx/soc.c | 76 +++++++++++++++++++ soc/arm/nxp_imx/rt5xx/usb.ld | 24 ++++++ 8 files changed, 121 insertions(+) create mode 100644 soc/arm/nxp_imx/rt5xx/usb.ld diff --git a/boards/arm/mimxrt595_evk/doc/index.rst b/boards/arm/mimxrt595_evk/doc/index.rst index a3d36cf8763..9c42be9704f 100644 --- a/boards/arm/mimxrt595_evk/doc/index.rst +++ b/boards/arm/mimxrt595_evk/doc/index.rst @@ -89,6 +89,8 @@ features: +-----------+------------+-------------------------------------+ | TRNG | on-chip | entropy | +-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts index 75243530052..8524a044b4f 100644 --- a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts +++ b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts @@ -205,6 +205,10 @@ arduino_serial: &flexcomm12 { status = "okay"; }; +zephyr_udc0: &usbhs { + status = "okay"; +}; + &ctimer0 { status = "okay"; }; diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml index 6bd71c8e87a..b9258634d35 100644 --- a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml +++ b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml @@ -23,4 +23,5 @@ supported: - gpio - i2c - spi + - usb_device - watchdog diff --git a/soc/arm/nxp_imx/rt5xx/CMakeLists.txt b/soc/arm/nxp_imx/rt5xx/CMakeLists.txt index 94661a7ccb1..d33dbceaa08 100644 --- a/soc/arm/nxp_imx/rt5xx/CMakeLists.txt +++ b/soc/arm/nxp_imx/rt5xx/CMakeLists.txt @@ -19,4 +19,7 @@ zephyr_library_include_directories( zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT5XX_BOOT_HEADER ROM_START SORT_KEY 0 boot_header.ld) +zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER + SECTIONS usb.ld) + zephyr_code_relocate(flash_clock_setup.c SRAM) diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 b/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 index f69100331a3..5fee31e7908 100644 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 +++ b/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 @@ -30,4 +30,12 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC endif # CORTEX_M_SYSTICK +config USB_MCUX + default y + depends on USB_DEVICE_DRIVER + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + endif # SOC_MIMXRT685S_CM33 diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.soc b/soc/arm/nxp_imx/rt5xx/Kconfig.soc index b1b8e941e61..d69e3c23e7d 100644 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.soc +++ b/soc/arm/nxp_imx/rt5xx/Kconfig.soc @@ -68,6 +68,9 @@ config SOC_PART_NUMBER_IMX_RT5XX option that you should not set directly. The part number selection choice defines the default value for this string. +config USB_DEDICATED_MEMORY + bool "Dedicated memory for USB transfer buffer and controller operation buffers" + menuconfig NXP_IMX_RT5XX_BOOT_HEADER bool "The boot header" depends on !BOOTLOADER_MCUBOOT diff --git a/soc/arm/nxp_imx/rt5xx/soc.c b/soc/arm/nxp_imx/rt5xx/soc.c index 42cb9ec1727..b42477caec2 100644 --- a/soc/arm/nxp_imx/rt5xx/soc.c +++ b/soc/arm/nxp_imx/rt5xx/soc.c @@ -18,6 +18,11 @@ #include "fsl_power.h" #include "fsl_clock.h" +#if CONFIG_USB_DC_NXP_LPCIP3511 +#include "usb_phy.h" +#include "usb_dc_mcux.h" +#endif + /* Board System oscillator settling time in us */ #define BOARD_SYSOSC_SETTLING_US 100U /* Board xtal frequency in Hz */ @@ -67,6 +72,13 @@ const clock_frg_clk_config_t g_frg12Config_clock_init = { .mult = 167 }; +#if CONFIG_USB_DC_NXP_LPCIP3511 +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + /* System clock frequency. */ extern uint32_t SystemCoreClock; @@ -116,6 +128,67 @@ __imx_boot_ivt_section void (* const image_vector_table[])(void) = { }; #endif /* CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */ +#if CONFIG_USB_DC_NXP_LPCIP3511 + +static void usb_device_clock_init(void) +{ + uint8_t usbClockDiv = 1; + uint32_t usbClockFreq; + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + /* Make sure USDHC ram buffer and usb1 phy has power up */ + POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); + POWER_DisablePD(kPDRUNCFG_LP_HSPAD_FSPI0_VDET); + POWER_ApplyPD(); + + RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); + + /* enable usb ip clock */ + CLOCK_EnableUsbHs0DeviceClock(kOSC_CLK_to_USB_CLK, usbClockDiv); + /* save usb ip clock freq*/ + usbClockFreq = g_xtalFreq / usbClockDiv; + CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4); + /* enable usb ram clock */ + CLOCK_EnableClock(kCLOCK_UsbhsSram); + /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ + CLOCK_EnableUsbHs0PhyPllClock(kOSC_CLK_to_USB_CLK, usbClockFreq); + + /* USB PHY initialization */ + USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL_SYS_CLK_HZ, &phyConfig); + +#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) + for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { + ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; + } +#endif + + /* The following code should run after phy initialization and should wait + * some microseconds to make sure utmi clock valid + */ + /* enable usb1 host clock */ + CLOCK_EnableClock(kCLOCK_UsbhsHost); + /* Wait until host_needclk de-asserts */ + while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { + __ASM("nop"); + } + /* According to reference mannual, device mode setting has to be set by access + * usb host register + */ + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + /* disable usb1 host clock */ + CLOCK_DisableClock(kCLOCK_UsbhsHost); +} + +#endif + void z_arm_platform_init(void) { /* This is provided by the SDK */ @@ -190,6 +263,9 @@ void clock_init(void) /* Switch FLEXCOMM0 to FRG */ CLOCK_AttachClk(kFRG_to_FLEXCOMM0); #endif +#if CONFIG_USB_DC_NXP_LPCIP3511 + usb_device_clock_init(); +#endif #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay) /* Switch FLEXCOMM4 to FRO_DIV4 */ CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM4); diff --git a/soc/arm/nxp_imx/rt5xx/usb.ld b/soc/arm/nxp_imx/rt5xx/usb.ld new file mode 100644 index 00000000000..13d76a9309e --- /dev/null +++ b/soc/arm/nxp_imx/rt5xx/usb.ld @@ -0,0 +1,24 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +GROUP_START(USB_BDT) + + SECTION_PROLOGUE(_USB_BDT_SECTION_NAME,(NOLOAD),) + { + . = ALIGN(512); + *(m_usb_bdt) + } GROUP_LINK_IN(SRAM1) + +GROUP_END(USB_BDT) + +GROUP_START(USB_GLOBAL) + + SECTION_PROLOGUE(_USB_GLOBAL_SECTION_NAME,(NOLOAD),) + { + *(m_usb_global) + } GROUP_LINK_IN(SRAM1) + +GROUP_END(USB_GLOBAL)