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drivers/clock_control: Enable ARC core support on quark_se driver

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Clock control can also be done through the ARC core.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2018-02-27 09:12:59 +01:00 committed by Carles Cufí
parent 423f0095c7
commit 29f8b23bfd
2 changed files with 39 additions and 29 deletions
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9
drivers/clock_control/Kconfig.quark_se
View File

@ -6,8 +6,6 @@
# SPDX-License-Identifier: Apache-2.0
#
if SOC_QUARK_SE_C1000
menuconfig CLOCK_CONTROL_QUARK_SE
bool
prompt "Quark SE Clock controller support"
@ -15,10 +13,11 @@ menuconfig CLOCK_CONTROL_QUARK_SE
help
Enable support for the Quark SE clock driver.
if CLOCK_CONTROL_QUARK_SE
config CLOCK_CONTROL_QUARK_SE_PERIPHERAL
bool
prompt "Quark SE peripheral clock support"
depends on CLOCK_CONTROL_QUARK_SE
default n
help
Enable support for Quark SE peripheral clock which controls the
@ -33,7 +32,6 @@ config CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config CLOCK_CONTROL_QUARK_SE_EXTERNAL
bool
prompt "Quark SE external clock support"
depends on CLOCK_CONTROL_QUARK_SE
default n
help
Enable support for Quark SE external sub-system clock.
@ -47,7 +45,6 @@ config CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME
config CLOCK_CONTROL_QUARK_SE_SENSOR
bool
prompt "Quark SE sensor clock support"
depends on CLOCK_CONTROL_QUARK_SE
default n
help
Enable support for Quark SE sensor sub-system clock.
@ -58,4 +55,4 @@ config CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
depends on CLOCK_CONTROL_QUARK_SE_SENSOR
default "clk_sensor"
endif # SOC_QUARK_SE_C1000
endif # CLOCK_CONTROL_QUARK_SE

59
drivers/clock_control/quark_se_clock_control.c
View File

@ -22,6 +22,18 @@
#define SYS_LOG_LEVEL CONFIG_SYS_LOG_CLOCK_CONTROL_LEVEL
#include <logging/sys_log.h>
#ifdef CONFIG_ARC
#define WRITE(__data, __base_address) \
sys_out32(__data, __base_address)
#define TEST_CLEAR_BIT(__base_address, __bit) \
sys_io_test_and_clear_bit(__base_address, __bit)
#else
#define WRITE(__data, __base_address) \
sys_write32(__data, __base_address)
#define TEST_CLEAR_BIT(__base_address, __bit) \
sys_test_and_clear_bit(__base_address, __bit)
#endif /* CONFIG_ARC */
struct quark_se_clock_control_config {
u32_t base_address;
};
@ -29,37 +41,39 @@ struct quark_se_clock_control_config {
static inline int quark_se_clock_control_on(struct device *dev,
clock_control_subsys_t sub_system)
{
const struct quark_se_clock_control_config *info = dev->config->config_info;
const struct quark_se_clock_control_config *info =
dev->config->config_info;
u32_t subsys = POINTER_TO_INT(sub_system);
if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) {
SYS_LOG_DBG("Enabling all clock gates on dev %p", dev);
sys_write32(0xffffffff, info->base_address);
WRITE(0xffffffff, info->base_address);
return 0;
}
SYS_LOG_DBG("Enabling clock gate on dev %p subsystem %u", dev, subsys);
return sys_test_and_set_bit(info->base_address, subsys);
return TEST_CLEAR_BIT(info->base_address, subsys);
}
static inline int quark_se_clock_control_off(struct device *dev,
clock_control_subsys_t sub_system)
{
const struct quark_se_clock_control_config *info = dev->config->config_info;
const struct quark_se_clock_control_config *info =
dev->config->config_info;
u32_t subsys = POINTER_TO_INT(sub_system);
if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) {
SYS_LOG_DBG("Disabling all clock gates on dev %p", dev);
sys_write32(0x00000000, info->base_address);
WRITE(0x00000000, info->base_address);
return 0;
}
SYS_LOG_DBG("clock gate on dev %p subsystem %u", dev, subsys);
return sys_test_and_clear_bit(info->base_address, subsys);
return TEST_CLEAR_BIT(info->base_address, subsys);
}
static const struct clock_control_driver_api quark_se_clock_control_api = {
@ -70,8 +84,7 @@ static const struct clock_control_driver_api quark_se_clock_control_api = {
int quark_se_clock_control_init(struct device *dev)
{
SYS_LOG_DBG("Quark Se clock controller driver initialized on device: "
"%p", dev);
SYS_LOG_DBG("Quark_SE clock controller on: %p", dev);
return 0;
}
@ -82,11 +95,11 @@ static struct quark_se_clock_control_config clock_quark_se_peripheral_config = {
};
DEVICE_AND_API_INIT(clock_quark_se_peripheral,
CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME,
&quark_se_clock_control_init,
NULL, &clock_quark_se_peripheral_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&quark_se_clock_control_api);
CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME,
&quark_se_clock_control_init,
NULL, &clock_quark_se_peripheral_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&quark_se_clock_control_api);
#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL */
#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL
@ -96,11 +109,11 @@ static struct quark_se_clock_control_config clock_quark_se_external_config = {
};
DEVICE_AND_API_INIT(clock_quark_se_external,
CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME,
&quark_se_clock_control_init,
NULL, &clock_quark_se_external_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&quark_se_clock_control_api);
CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME,
&quark_se_clock_control_init,
NULL, &clock_quark_se_external_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&quark_se_clock_control_api);
#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL */
#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR
@ -110,10 +123,10 @@ static struct quark_se_clock_control_config clock_quark_se_sensor_config = {
};
DEVICE_AND_API_INIT(clock_quark_se_sensor,
CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME,
&quark_se_clock_control_init,
NULL, &clock_quark_se_sensor_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&quark_se_clock_control_api);
CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME,
&quark_se_clock_control_init,
NULL, &clock_quark_se_sensor_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&quark_se_clock_control_api);
#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR */