From 24eb735b244b2567a4b745d69fed36ece47d9b41 Mon Sep 17 00:00:00 2001 From: McAtee Maxwell Date: Wed, 22 Jan 2025 12:32:26 -0800 Subject: [PATCH] adc: modifications to support adc on cyw920829m2evk_02 platform - Modifications to adc driver - Modifications to clock_control driver - Add adc to board's yaml - Add adc to relevant dts file Signed-off-by: McAtee Maxwell --- .../cyw920829m2evk_02/cyw920829m2evk_02.yaml | 1 + drivers/adc/adc_ifx_cat1.c | 91 ++++++++++++++----- .../clock_control/clock_control_ifx_cat1.c | 7 ++ dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi | 8 ++ 4 files changed, 83 insertions(+), 24 deletions(-) diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml index 9d83de725c0..3244d698080 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml @@ -17,6 +17,7 @@ supported: - uart - clock_control - bluetooth + - adc - watchdog - spi - i2c diff --git a/drivers/adc/adc_ifx_cat1.c b/drivers/adc/adc_ifx_cat1.c index e247ee96209..0df730d1433 100644 --- a/drivers/adc/adc_ifx_cat1.c +++ b/drivers/adc/adc_ifx_cat1.c @@ -22,9 +22,11 @@ LOG_MODULE_REGISTER(ifx_cat1_adc, CONFIG_ADC_LOG_LEVEL); #if defined(PASS_SARMUX_PADS0_PORT) - #define _ADCSAR_PORT PASS_SARMUX_PADS0_PORT +#define _ADC_PORT PASS_SARMUX_PADS0_PORT +#elif defined(ADCMIC_GPIO_ADC_IN0_PORT) +#define _ADC_PORT ADCMIC_GPIO_ADC_IN0_PORT #else - #error The selected device does not supported ADC +#error The selected device does not supported ADC #endif #define ADC_CAT1_EVENTS_MASK (CYHAL_ADC_EOS | CYHAL_ADC_ASYNC_READ_COMPLETE) @@ -33,15 +35,25 @@ LOG_MODULE_REGISTER(ifx_cat1_adc, CONFIG_ADC_LOG_LEVEL); #define ADC_CAT1_RESOLUTION (12u) #define ADC_CAT1_REF_INTERNAL_MV (1200u) +#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) +#define IFX_ADC_NUM_CHANNELS \ + ARRAY_SIZE(cyhal_pin_map_adcmic_gpio_adc_in) +#else +#define IFX_ADC_NUM_CHANNELS CY_SAR_SEQ_NUM_CHANNELS +#endif + struct ifx_cat1_adc_data { struct adc_context ctx; const struct device *dev; cyhal_adc_t adc_obj; - cyhal_adc_channel_t adc_chan_obj[CY_SAR_SEQ_NUM_CHANNELS]; + cyhal_adc_channel_t adc_chan_obj[IFX_ADC_NUM_CHANNELS]; uint16_t *buffer; uint16_t *repeat_buffer; uint32_t channels; uint32_t channels_mask; +#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B + struct k_work adc_worker_thread; +#endif }; struct ifx_cat1_adc_config { @@ -74,13 +86,42 @@ static void _cyhal_adc_event_callback(void *callback_arg, cyhal_adc_event_t even LOG_DBG("%s ISR triggered.", dev->name); } +#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B +static void ifx_cat1_adc_worker(struct k_work *adc_worker_thread) +{ + struct ifx_cat1_adc_data *data = + CONTAINER_OF(adc_worker_thread, struct ifx_cat1_adc_data, adc_worker_thread); + + uint32_t channels = data->channels; + int32_t result; + uint32_t channel_id; + + while (channels != 0) { + channel_id = find_lsb_set(channels) - 1; + channels &= ~BIT(channel_id); + + result = cyhal_adc_read(&data->adc_chan_obj[channel_id]); + /* Legacy API for BWC. Convert from signed to unsigned by adding 0x800 to + * convert the lowest signed 12-bit number to 0x0. + */ + *data->buffer = (uint16_t)(result + 0x800); + data->buffer++; + } + adc_context_on_sampling_done(&data->ctx, data->dev); +} +#endif + static void adc_context_start_sampling(struct adc_context *ctx) { struct ifx_cat1_adc_data *data = CONTAINER_OF(ctx, struct ifx_cat1_adc_data, ctx); data->repeat_buffer = data->buffer; +#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) + k_work_submit(&data->adc_worker_thread); +#else Cy_SAR_StartConvert(data->adc_obj.base, CY_SAR_START_CONVERT_SINGLE_SHOT); +#endif } static void adc_context_update_buffer_pointer(struct adc_context *ctx, @@ -99,10 +140,10 @@ static int ifx_cat1_adc_channel_setup(const struct device *dev, struct ifx_cat1_adc_data *data = dev->data; cy_rslt_t result; - cyhal_gpio_t vplus = CYHAL_GET_GPIO(_ADCSAR_PORT, channel_cfg->input_positive); - cyhal_gpio_t vminus = channel_cfg->differential ? - CYHAL_GET_GPIO(_ADCSAR_PORT, channel_cfg->input_negative) : - CYHAL_ADC_VNEG; + cyhal_gpio_t vplus = CYHAL_GET_GPIO(_ADC_PORT, channel_cfg->input_positive); + cyhal_gpio_t vminus = channel_cfg->differential + ? CYHAL_GET_GPIO(_ADC_PORT, channel_cfg->input_negative) + : CYHAL_ADC_VNEG; uint32_t acquisition_ns = ADC_CAT1_DEFAULT_ACQUISITION_NS; if (channel_cfg->reference != ADC_REF_INTERNAL) { @@ -158,7 +199,7 @@ static int validate_buffer_size(const struct adc_sequence *sequence) int active_channels = 0; int total_buffer_size; - for (int i = 0; i < CY_SAR_SEQ_NUM_CHANNELS; i++) { + for (int i = 0; i < IFX_ADC_NUM_CHANNELS; i++) { if (sequence->channels & BIT(i)) { active_channels++; } @@ -250,7 +291,7 @@ static int ifx_cat1_adc_init(const struct device *dev) data->dev = dev; /* Initialize ADC. The ADC block which can connect to the input pin is selected */ - result = cyhal_adc_init(&data->adc_obj, CYHAL_GET_GPIO(_ADCSAR_PORT, 0), NULL); + result = cyhal_adc_init(&data->adc_obj, CYHAL_GET_GPIO(_ADC_PORT, 0), NULL); if (result != CY_RSLT_SUCCESS) { LOG_ERR("ADC initialization failed. Error: 0x%08X\n", (unsigned int)result); return -EIO; @@ -274,23 +315,25 @@ static DEVICE_API(adc, adc_cat1_driver_api) = { #endif .ref_internal = ADC_CAT1_REF_INTERNAL_MV }; +#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B +#define ADC_WORKER_THREAD_INIT() .adc_worker_thread = Z_WORK_INITIALIZER(ifx_cat1_adc_worker), +#else +#define ADC_WORKER_THREAD_INIT() +#endif /* Macros for ADC instance declaration */ -#define INFINEON_CAT1_ADC_INIT(n) \ - static struct ifx_cat1_adc_data ifx_cat1_adc_data##n = { \ - ADC_CONTEXT_INIT_TIMER(ifx_cat1_adc_data##n, ctx), \ - ADC_CONTEXT_INIT_LOCK(ifx_cat1_adc_data##n, ctx), \ - ADC_CONTEXT_INIT_SYNC(ifx_cat1_adc_data##n, ctx), \ - }; \ - \ - static const struct ifx_cat1_adc_config adc_cat1_cfg_##n = { \ - .irq_priority = DT_INST_IRQ(n, priority), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, ifx_cat1_adc_init, \ - NULL, &ifx_cat1_adc_data##n, \ - &adc_cat1_cfg_##n, \ - POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \ +#define INFINEON_CAT1_ADC_INIT(n) \ + static struct ifx_cat1_adc_data ifx_cat1_adc_data##n = { \ + ADC_CONTEXT_INIT_TIMER(ifx_cat1_adc_data##n, ctx), \ + ADC_CONTEXT_INIT_LOCK(ifx_cat1_adc_data##n, ctx), \ + ADC_CONTEXT_INIT_SYNC(ifx_cat1_adc_data##n, ctx), ADC_WORKER_THREAD_INIT()}; \ + \ + static const struct ifx_cat1_adc_config adc_cat1_cfg_##n = { \ + .irq_priority = DT_INST_IRQ(n, priority), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, ifx_cat1_adc_init, NULL, &ifx_cat1_adc_data##n, \ + &adc_cat1_cfg_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \ &adc_cat1_driver_api); DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_ADC_INIT) diff --git a/drivers/clock_control/clock_control_ifx_cat1.c b/drivers/clock_control/clock_control_ifx_cat1.c index 7ed8493131c..071eb0e9559 100644 --- a/drivers/clock_control/clock_control_ifx_cat1.c +++ b/drivers/clock_control/clock_control_ifx_cat1.c @@ -533,9 +533,16 @@ static int clock_control_infineon_cat1_init(const struct device *dev) clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf3)); clock_div = DT_PROP(DT_NODELABEL(clk_hf3), clock_div); +#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) && \ + defined(CONFIG_USE_INFINEON_ADC) + Cy_SysClk_ClkHfSetSource(3, CY_SYSCLK_CLKHF_IN_CLKPATH1); + Cy_SysClk_ClkHfSetDivider(3, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(3); +#else if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[3], clock_div)) { return -EIO; } +#endif #endif /* Configure the HF[4] to source defined in tree device 'clk_hf4' node */ diff --git a/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi b/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi index 763eca835d2..69ef3d0fbf6 100644 --- a/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi +++ b/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi @@ -113,6 +113,14 @@ #gpio-cells = <2>; }; + adc0: adc@40520000 { + compatible = "infineon,cat1-adc"; + reg = <0x40520000 0x10000>; + interrupts = <67 6>; + status = "disabled"; + #io-channel-cells = <1>; + }; + ipc0: ipc@401d0000 { compatible = "infineon,cat1-ipc"; reg = <0x401d0000 0x10000>;