diff --git a/boards/nuvoton/npck3m8k_evb/Kconfig.defconfig b/boards/nuvoton/npck3m8k_evb/Kconfig.defconfig new file mode 100644 index 00000000000..dea8842cad1 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/Kconfig.defconfig @@ -0,0 +1,2 @@ +# Copyright (c) 2025 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/nuvoton/npck3m8k_evb/Kconfig.npck3m8k_evb b/boards/nuvoton/npck3m8k_evb/Kconfig.npck3m8k_evb new file mode 100644 index 00000000000..8864c728b79 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/Kconfig.npck3m8k_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCK3M8K_EVB + select SOC_NPCK3M8K diff --git a/boards/nuvoton/npck3m8k_evb/board.yml b/boards/nuvoton/npck3m8k_evb/board.yml new file mode 100644 index 00000000000..5095987b7fa --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: npck3m8k_evb + full_name: NPCK3M8K_EVB + vendor: nuvoton + socs: + - name: npck3m8k diff --git a/boards/nuvoton/npck3m8k_evb/doc/index.rst b/boards/nuvoton/npck3m8k_evb/doc/index.rst new file mode 100644 index 00000000000..753842dc6a6 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/doc/index.rst @@ -0,0 +1,60 @@ +.. zephyr:board:: npck3m8k_evb + +Overview +******** + +The NPCK3M8K_EVB kit is a development platform to evaluate the +Nuvoton NPCK3 series microcontrollers. This board is designed to provide +a range of peripherals and interfaces for development and testing. It needs +to be mated with part number NPCK3M8K. + +Hardware +******** + +- ARM Cortex-M4F Processor +- 352 KB RAM and 64 KB boot ROM +- GPIO headers +- UART0 and UART1 +- JTAG interface + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The NPCK3M8K MCU is configured to use the 90Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock +control register (chapter 4 in user manual) + +Serial Port +=========== + +UART1 is configured for serial logs. + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Flashing +======== + +Build the application as usual for the ``npck3m8k_evb`` board. + +Debugging +========= + +Use JTAG/SWD with a J-Link. + +References +********** + +.. target-notes:: diff --git a/boards/nuvoton/npck3m8k_evb/doc/npck3m8k_evb.webp b/boards/nuvoton/npck3m8k_evb/doc/npck3m8k_evb.webp new file mode 100644 index 00000000000..5ea00e2a859 Binary files /dev/null and b/boards/nuvoton/npck3m8k_evb/doc/npck3m8k_evb.webp differ diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb-pinctrl.dtsi b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb-pinctrl.dtsi new file mode 100644 index 00000000000..62e812975ec --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb-pinctrl.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts new file mode 100644 index 00000000000..d03c6333535 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "npck3m8k_evb-pinctrl.dtsi" + +/ { + model = "Nuvoton NPCK3M8K evaluation board"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,flash = &flash0; + zephyr,keyboard-scan = &kscan_input; + }; + + aliases { + /* For samples/basic/blinky_pwm */ + pwm-led0 = &pwm_led0_green; + + /* For gpio test suites */ + led0 = &gpio_led_red; + + /* For pwm test suites */ + pwm-0 = &pwmb; + + /* For i2c test suites */ + i2c-0 = &i2c1_a; + + /* For watchdog sample */ + watchdog0 = &twd0; + + /* For peci driver sample code */ + peci-0 = &peci0; + + /* For kscan test suites */ + kscan0 = &kscan_input; + }; + + leds-pwm { + compatible = "pwm-leds"; + + pwm_led0_green: pwm_led_0 { + pwms = <&pwmb 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "User D7 green"; + }; + }; + + leds-gpio { + compatible = "gpio-leds"; + + gpio_led_red: led_0 { + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; + label = "User D8 red"; + }; + }; +}; + +&cpu0 { + cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>; +}; + +/* Overwrite default device properties with overlays in board dt file here. */ + +&qspi_fiu0 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + + /* Use UART1_SL1 ie. PIN83.88 */ + pinctrl-0 = <&uart1_sin_gp87 + &uart1_sout_gp83>; + pinctrl-names = "default"; +}; + +&pwmb { + status = "okay"; + pinctrl-0 = <&pwmb_gp21>; + pinctrl-names = "default"; +}; + +&adc0 { + status = "disabled"; + + /* Use adc0 channel 0 and 2 for 'adc_api' driver tests */ + pinctrl-0 = <&adc0_chan0_gp90 + &adc0_chan2_gp92>; + pinctrl-names = "default"; +}; + +&espi0 { + status = "disabled"; + pinctrl-0 = <&espi_lpc_gp10_f7>; + pinctrl-names = "default"; +}; + +&i2c1_a { + status = "disabled"; + pinctrl-0 = <&i2c1_a_sda_scl_gp22_17>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&i2c_ctrl1 { + status = "disabled"; +}; + +&tach1 { + status = "okay"; + pinctrl-0 = <&ta1_1_in_gp56>; + pinctrl-names = "default"; + port = ; /* port-A is selected */ + sample-clk = ; /* Use LFCLK as sampling clock */ + pulses-per-round = <1>; /* number of pulses per round of encoder */ +}; + +&peci0 { + status = "okay"; + pinctrl-0 = <>; + pinctrl-names = "default"; +}; + +&kbd { + /* Demonstrate a 13 x 8 keyboard matrix on evb */ + pinctrl-0 = <&ksi0_1_2_3_gpa0_a1_a2_a3 /* KSI0/1/2/3 PINA0/A1/A2/A3 */ + &ksi4_5_gpa4_a5 /* KSI4/5 PINA4/A5 */ + &ksi6_7_gpa6_a7 /* KSI6/7 PINA6/A7 */ + &kso00_01_02_03_gpb0_b1_b2_b3 /* KSO00/01/02/03 PINB0/B1/B2/B3 */ + &kso04_05_06_07_gpb4_b5_b6_b7 /* KS004/05/06/07 PINB4/B5/B6/B7 */ + &kso08_09_gpc0_c1 /* KSO08/09 PINC0/C1 */ + &kso10_11_gpc2_c3 /* KSO10/11 PINC2/C3 */ + &kso12_gp64 /* KSO12 PIN64 */ + >; + pinctrl-names = "default"; + row-size = <8>; + col-size = <13>; + status = "okay"; + + kscan_input: kscan-input { + compatible = "zephyr,kscan-input"; + }; +}; diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.yaml b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.yaml new file mode 100644 index 00000000000..c39728c2c5c --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2022 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: npck3m8k_evb +name: Nuvoton NPCK3M8K EVB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 64 +flash: 192 +supported: + - clock + - gpio + - uart diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb_defconfig b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb_defconfig new file mode 100644 index 00000000000..c1a473d497f --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb_defconfig @@ -0,0 +1,28 @@ +# +# Copyright (c) 2025 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 +# + +# Enable NPCX firmware header +CONFIG_NPCX_HEADER=y +CONFIG_NPCX_IMAGE_OUTPUT_HEX=y +CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y +CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# UART Driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# GPIO Driver +CONFIG_GPIO=y + +# Console Driver +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nuvoton/npck3m8k_evb/support/openocd.cfg b/boards/nuvoton/npck3m8k_evb/support/openocd.cfg new file mode 100644 index 00000000000..6e70e381f41 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/support/openocd.cfg @@ -0,0 +1,16 @@ +# script for Nuvoton NPCX Cortex-M4 Series + +source [find interface/jlink.cfg] +transport select swd + +set CHIPNAME npcx_v2 +set FIUNAME npck.fiu +source [find target/npcx.cfg] + +proc npcx_write_image {target_image} { + flash write_image erase $target_image 0x64000000 ihex +} + +proc npcx_verify_image {target_image} { + verify_image $target_image 0x64000000 ihex +} diff --git a/soc/nuvoton/npcx/npck3/Kconfig.defconfig b/soc/nuvoton/npcx/npck3/Kconfig.defconfig index 8d9ec64cb88..4ab107bc593 100644 --- a/soc/nuvoton/npcx/npck3/Kconfig.defconfig +++ b/soc/nuvoton/npcx/npck3/Kconfig.defconfig @@ -18,4 +18,7 @@ config ESPI_TAF_NPCX config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_nodelabel_int_prop,itims,clock-frequency) +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + endif # SOC_SERIES_NPCK3 diff --git a/tests/drivers/adc/adc_api/boards/npck3m8k_evb.overlay b/tests/drivers/adc/adc_api/boards/npck3m8k_evb.overlay new file mode 100644 index 00000000000..5614d545114 --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/npck3m8k_evb.overlay @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 Benjamin Björnsson + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + zephyr,user { + io-channels = <&adc0 0>, <&adc0 2>; + }; +}; + +&adc0 { + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <10>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <10>; + }; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/npck3m8k_evb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/npck3m8k_evb.overlay new file mode 100644 index 00000000000..e48379157f5 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/npck3m8k_evb.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpioh 2 0>; /* GPIO header A12 */ + in-gpios = <&gpioh 1 0>; /* GPIO header B12 */ + }; +};