dts: arm64: nxp: add device tree for i.MX95 Cortex-M7
Added device tree file for i.MX95 Cortex-M7 and added i.MX95 clock ID header file. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Yangbo Lu
Alberto Escolar
parent
5bec2a3dde
commit
20cde899bf
154
dts/arm/nxp/nxp_imx95_m7.dtsi
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154
dts/arm/nxp/nxp_imx95_m7.dtsi
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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/imx95_clock.h>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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scmi_shmem0: memory@44611000 {
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compatible = "arm,scmi-shmem";
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reg = <0x44611000 0x80>;
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};
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};
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firmware {
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scmi {
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compatible = "arm,scmi";
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shmem = <&scmi_shmem0>;
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mboxes = <&mu5 0>;
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mbox-names = "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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compatible = "arm,scmi-clock";
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_iomuxc: protocol@19 {
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compatible = "arm,scmi-pinctrl";
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reg = <0x19>;
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pinctrl: pinctrl {
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compatible = "nxp,imx95-pinctrl", "nxp,imx93-pinctrl";
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};
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};
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};
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};
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soc {
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itcm: itcm@0 {
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compatible = "nxp,imx-itcm";
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reg = <0x0 DT_SIZE_K(256)>;
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};
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dtcm: dtcm@20000000 {
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compatible = "nxp,imx-dtcm";
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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lpuart3: serial@42570000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x42570000 DT_SIZE_K(64)>;
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interrupts = <64 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART3>;
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status = "disabled";
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};
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lpuart4: serial@42580000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x42580000 DT_SIZE_K(64)>;
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interrupts = <65 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART4>;
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status = "disabled";
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};
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lpuart5: serial@42590000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x42590000 DT_SIZE_K(64)>;
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interrupts = <66 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART5>;
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status = "disabled";
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};
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lpuart6: serial@425a0000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x425a0000 DT_SIZE_K(64)>;
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interrupts = <67 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART6>;
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status = "disabled";
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};
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lpuart7: serial@42690000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x42690000 DT_SIZE_K(64)>;
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interrupts = <68 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART7>;
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status = "disabled";
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};
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lpuart8: serial@426a0000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x426a0000 DT_SIZE_K(64)>;
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interrupts = <69 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART8>;
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status = "disabled";
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};
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lpuart1: serial@44380000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x44380000 DT_SIZE_K(64)>;
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interrupts = <19 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART1>;
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status = "disabled";
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};
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lpuart2: serial@44390000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x44390000 DT_SIZE_K(64)>;
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interrupts = <20 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART2>;
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status = "disabled";
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};
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mu5: mailbox@44610000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x44610000 DT_SIZE_K(4)>;
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interrupts = <205 0>;
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#mbox-cells = <1>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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177
include/zephyr/dt-bindings/clock/imx95_clock.h
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177
include/zephyr/dt-bindings/clock/imx95_clock.h
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@ -0,0 +1,177 @@
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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_
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#define IMX95_CLK_32K 1
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#define IMX95_CLK_24M 2
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#define IMX95_CLK_FRO 3
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#define IMX95_CLK_SYSPLL1_VCO 4
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#define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5
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#define IMX95_CLK_SYSPLL1_PFD0 6
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#define IMX95_CLK_SYSPLL1_PFD0_DIV2 7
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#define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8
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#define IMX95_CLK_SYSPLL1_PFD1 9
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#define IMX95_CLK_SYSPLL1_PFD1_DIV2 10
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#define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11
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#define IMX95_CLK_SYSPLL1_PFD2 12
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#define IMX95_CLK_SYSPLL1_PFD2_DIV2 13
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#define IMX95_CLK_AUDIOPLL1_VCO 14
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#define IMX95_CLK_AUDIOPLL1 15
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#define IMX95_CLK_AUDIOPLL2_VCO 16
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#define IMX95_CLK_AUDIOPLL2 17
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#define IMX95_CLK_VIDEOPLL1_VCO 18
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#define IMX95_CLK_VIDEOPLL1 19
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#define IMX95_CLK_RESERVED20 20
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#define IMX95_CLK_RESERVED21 21
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#define IMX95_CLK_RESERVED22 22
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#define IMX95_CLK_RESERVED23 23
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#define IMX95_CLK_ARMPLL_VCO 24
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#define IMX95_CLK_ARMPLL_PFD0_UNGATED 25
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#define IMX95_CLK_ARMPLL_PFD0 26
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#define IMX95_CLK_ARMPLL_PFD1_UNGATED 27
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#define IMX95_CLK_ARMPLL_PFD1 28
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#define IMX95_CLK_ARMPLL_PFD2_UNGATED 29
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#define IMX95_CLK_ARMPLL_PFD2 30
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#define IMX95_CLK_ARMPLL_PFD3_UNGATED 31
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#define IMX95_CLK_ARMPLL_PFD3 32
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#define IMX95_CLK_DRAMPLL_VCO 33
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#define IMX95_CLK_DRAMPLL 34
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#define IMX95_CLK_HSIOPLL_VCO 35
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#define IMX95_CLK_HSIOPLL 36
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#define IMX95_CLK_LDBPLL_VCO 37
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#define IMX95_CLK_LDBPLL 38
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#define IMX95_CLK_EXT1 39
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#define IMX95_CLK_EXT2 40
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#define IMX95_CCM_NUM_CLK_SRC 41
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#define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0)
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#define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1)
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#define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2)
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#define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3)
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#define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4)
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#define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5)
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#define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6)
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#define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7)
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#define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8)
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#define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9)
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#define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10)
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#define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11)
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#define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12)
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#define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13)
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#define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14)
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#define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15)
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#define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16)
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#define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17)
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#define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18)
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#define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19)
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#define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20)
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#define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21)
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#define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22)
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#define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23)
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#define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24)
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#define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25)
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#define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26)
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#define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27)
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#define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28)
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#define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29)
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#define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30)
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#define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31)
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#define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32)
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#define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33)
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#define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34)
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#define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35)
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#define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36)
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#define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37)
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#define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38)
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#define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39)
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#define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40)
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#define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41)
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#define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42)
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#define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43)
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#define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44)
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#define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45)
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#define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46)
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#define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47)
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#define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48)
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#define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49)
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#define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50)
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#define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51)
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#define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52)
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#define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53)
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#define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54)
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#define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55)
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#define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56)
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#define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57)
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#define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58)
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#define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59)
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#define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60)
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#define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61)
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#define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62)
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#define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63)
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#define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64)
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#define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65)
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#define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66)
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#define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67)
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#define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68)
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#define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69)
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#define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70)
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#define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71)
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#define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72)
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#define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73)
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#define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74)
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#define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75)
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#define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76)
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#define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77)
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#define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78)
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#define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79)
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#define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80)
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#define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81)
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#define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82)
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#define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83)
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#define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84)
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#define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85)
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#define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86)
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#define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87)
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#define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88)
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#define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89)
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#define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90)
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#define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91)
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#define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92)
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#define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93)
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#define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94)
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#define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95)
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#define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96)
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#define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97)
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#define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98)
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#define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99)
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#define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100)
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#define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101)
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#define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102)
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#define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103)
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#define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104)
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#define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105)
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#define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106)
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#define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107)
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#define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108)
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#define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109)
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#define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110)
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#define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111)
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#define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112)
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#define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113)
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#define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114)
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#define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115)
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#define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116)
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#define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117)
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#define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118)
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#define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119)
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#define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120)
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#define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121)
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#define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_ */
|
||||
Loading…
Reference in New Issue
Block a user