From 1a583e44baafc41a63d0bc9eeecfde5699a4e019 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 13 May 2021 15:29:06 +0200 Subject: [PATCH] arch: arm: cortex_m: fix D-Cache reset with CONFIG_INIT_ARCH_HW_AT_BOOT On reset we do not know what is the status of the D-Cache, nor its content. If it is disabled, do not try to clean it, as it might contains random data for random addresses, and this might just create a bus fault. Invalidating it is enough. If it is enabled, it means its content is not random. SCB_InvalidateDCache() will clean it, invalidate it and disable it. Signed-off-by: Aurelien Jarno --- arch/arm/core/aarch32/cortex_m/scb.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/core/aarch32/cortex_m/scb.c b/arch/arm/core/aarch32/cortex_m/scb.c index f310d247168..aa5e9db6491 100644 --- a/arch/arm/core/aarch32/cortex_m/scb.c +++ b/arch/arm/core/aarch32/cortex_m/scb.c @@ -93,9 +93,17 @@ void z_arm_init_arch_hw_at_boot(void) } #if defined(CONFIG_CPU_CORTEX_M7) - /* Reset Cache settings */ - SCB_CleanInvalidateDCache(); - SCB_DisableDCache(); + /* Reset D-Cache settings. If the D-Cache was enabled, + * SCB_DisableDCache() takes care of cleaning and invalidating it. + * If it was already disabled, just call SCB_InvalidateDCache() to + * reset it to a known clean state. + */ + if (SCB->CCR & SCB_CCR_DC_Msk) { + SCB_DisableDCache(); + } else { + SCB_InvalidateDCache(); + } + /* Reset I-Cache settings. */ SCB_DisableICache(); #endif /* CONFIG_CPU_CORTEX_M7 */