esp32: drivers: pinmux: code refactoring
to make use of Espressif's hal in order to ease both driver maintenance and code reuse between socs. Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
This commit is contained in:
Glauber Maroto Ferreira
Anas Nashif
parent
8b13046cb6
commit
17f3792abf
@ -280,6 +280,7 @@
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/drivers/pinmux/*b91* @yurvyn
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/drivers/pinmux/*hsdk* @iriszzw
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/drivers/pinmux/*it8xxx2* @ite
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/drivers/pinmux/*esp32* @glaubermaroto
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/drivers/pm_cpu_ops/ @carlocaione
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/drivers/ps2/ @franciscomunoz @scottwcpg
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/drivers/ps2/*xec* @franciscomunoz @scottwcpg
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,100 +8,35 @@
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#define DT_DRV_COMPAT espressif_esp32_pinmux
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <soc/gpio_reg.h>
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#include <soc/io_mux_reg.h>
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#include <soc/soc.h>
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#include <hal/gpio_types.h>
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#include <hal/gpio_ll.h>
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#include <errno.h>
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#include <sys/util.h>
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#include <drivers/pinmux.h>
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/* DR_REG_IO_MUX_BASE is a 32-bit constant. Define a pin mux table
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* using only offsets, in order to reduce ROM footprint.
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* This table has been compiled from information present in "ESP32
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* Technical Reference Manual", "IO_MUX Pad List". The items in
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* this array covers only the first function of each I/O pin.
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* Items with offset `0` are not present in the documentation, and
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* trying to configure them will result in -EINVAL being returned.
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*
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* Note: DR_REG_IO_MUX_BASE here is used to extract GPIO_X register offset.
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* Don't replace it by device tree value, because PERIPHS_IO_MUX_
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* is "internally" depends on it.
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*/
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#define PIN(id) ((PERIPHS_IO_MUX_ ## id ## _U) - (DR_REG_IO_MUX_BASE))
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static const uint8_t pin_mux_off[] = {
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PIN(GPIO0), PIN(U0TXD), PIN(GPIO2), PIN(U0RXD),
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PIN(GPIO4), PIN(GPIO5), PIN(SD_CLK), PIN(SD_DATA0),
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PIN(SD_DATA1), PIN(SD_DATA2), PIN(SD_DATA3), PIN(SD_CMD),
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PIN(MTDI), PIN(MTCK), PIN(MTMS), PIN(MTDO),
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PIN(GPIO16), PIN(GPIO17), PIN(GPIO18), PIN(GPIO19),
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0, PIN(GPIO21), PIN(GPIO22), PIN(GPIO23),
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0, PIN(GPIO25), PIN(GPIO26), PIN(GPIO27),
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0, 0, 0, 0,
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PIN(GPIO32), PIN(GPIO33), PIN(GPIO34), PIN(GPIO35),
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PIN(GPIO36), PIN(GPIO37), PIN(GPIO38), PIN(GPIO39)
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};
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#undef PIN
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static uint32_t *reg_for_pin(uint32_t pin)
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{
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uint8_t off;
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if (pin >= ARRAY_SIZE(pin_mux_off)) {
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return NULL;
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}
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off = pin_mux_off[pin];
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if (!off) {
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return NULL;
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}
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return (uint32_t *)(DT_INST_REG_ADDR(0) + off);
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}
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static int set_reg(uint32_t pin, uint32_t clr_mask, uint32_t set_mask)
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{
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volatile uint32_t *reg = reg_for_pin(pin);
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uint32_t v;
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if (!reg) {
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return -EINVAL;
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}
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v = *reg;
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v &= ~clr_mask;
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v |= set_mask;
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*reg = v;
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return 0;
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}
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static int pinmux_set(const struct device *dev, uint32_t pin, uint32_t func)
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{
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ARG_UNUSED(dev);
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/* FIXME: Drive strength (FUN_DRV) is also set here to its maximum
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* value due to a deficiency in the pinmux API. This setting is
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* part of the GPIO API.
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*/
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if (func > 6) {
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if ((func > PINMUX_FUNC_G) || (pin >= GPIO_NUM_MAX)) {
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return -EINVAL;
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}
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return set_reg(pin, MCU_SEL_M, func<<MCU_SEL_S | 2<<FUN_DRV_S);
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gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[pin], func);
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return 0;
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}
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static int pinmux_get(const struct device *dev, uint32_t pin, uint32_t *func)
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{
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ARG_UNUSED(dev);
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volatile uint32_t *reg = reg_for_pin(pin);
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if (!reg) {
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if (pin >= GPIO_NUM_MAX) {
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return -EINVAL;
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}
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*func = (*reg & MCU_SEL_M) >> MCU_SEL_S;
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*func = REG_GET_FIELD(GPIO_PIN_MUX_REG[pin], MCU_SEL);
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return 0;
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}
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@ -111,54 +47,35 @@ static int pinmux_pullup(const struct device *dev, uint32_t pin, uint8_t func)
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switch (func) {
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case PINMUX_PULLUP_DISABLE:
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return set_reg(pin, FUN_PU, FUN_PD);
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gpio_ll_pullup_dis(&GPIO, pin);
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break;
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case PINMUX_PULLUP_ENABLE:
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return set_reg(pin, FUN_PD, FUN_PU);
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gpio_ll_pullup_en(&GPIO, pin);
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break;
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default:
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return -EINVAL;
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}
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return -EINVAL;
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return 0;
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}
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#define CFG(id) ((GPIO_ ## id ## _REG) & 0xff)
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static int pinmux_input(const struct device *dev, uint32_t pin, uint8_t func)
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{
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ARG_UNUSED(dev);
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static const uint8_t offs[2][3] = {
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{ CFG(ENABLE1_W1TC), CFG(ENABLE1_W1TS), 32 },
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{ CFG(ENABLE_W1TC), CFG(ENABLE_W1TS), 0 },
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};
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const uint8_t *line = offs[pin < 32];
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volatile uint32_t *reg;
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int r;
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/* Since PINMUX_INPUT_ENABLED == 1 and PINMUX_OUTPUT_ENABLED == 0,
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* we can not set a gpio port as input and output at the same time,
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* So we always set the gpio as input. Thus, the gpio can be used on
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* I2C drivers for example.
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*/
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r = set_reg(pin, 0, FUN_IE);
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if (func == PINMUX_INPUT_ENABLED) {
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reg = (uint32_t *)(DR_REG_GPIO_BASE + line[0]);
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} else if (func == PINMUX_OUTPUT_ENABLED) {
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if (pin >= 34U && pin <= 39U) {
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/* These pins are input only */
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return -EINVAL;
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}
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reg = (uint32_t *)(DR_REG_GPIO_BASE + line[1]);
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} else {
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switch (func) {
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case PINMUX_INPUT_ENABLED:
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gpio_ll_input_enable(&GPIO, pin);
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break;
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case PINMUX_OUTPUT_ENABLED:
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gpio_ll_output_enable(&GPIO, pin);
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break;
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default:
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return -EINVAL;
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}
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if (r < 0) {
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return r;
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}
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*reg = BIT(pin - line[2]);
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return 0;
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}
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#undef CFG
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static struct pinmux_driver_api api_funcs = {
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.set = pinmux_set,
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@ -171,15 +88,6 @@ static int pinmux_initialize(const struct device *dev)
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{
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ARG_UNUSED(dev);
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#if !CONFIG_BOOTLOADER_ESP_IDF
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uint32_t pin;
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for (pin = 0U; pin < ARRAY_SIZE(pin_mux_off); pin++) {
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pinmux_set(NULL, pin, 0);
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}
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#endif
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return 0;
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}
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