From 0787936d15b5058d90ea71de8a0ecff677aebe83 Mon Sep 17 00:00:00 2001
From: Andrei Gansari <andrei.gansari@nxp.com>
Date: Thu, 31 Jan 2019 13:00:56 +0200
Subject: [PATCH] mimxrt1050_evk: eth_mcux: driver fixup

Boot PHY initialization timeout, caching mechanism fixes and networking
buffer descriptors moved to no cache section. Enabled cache management
in networking driver and manual barriers.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
---
 boards/arm/mimxrt1050_evk/pinmux.c          | 17 +++++++++++++++--
 drivers/ethernet/eth_mcux.c                 |  9 +++++++++
 ext/hal/nxp/mcux/drivers/imx/fsl_enet.c     |  3 +++
 ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c |  2 ++
 4 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/boards/arm/mimxrt1050_evk/pinmux.c b/boards/arm/mimxrt1050_evk/pinmux.c
index b0f67ba5a95..182c22f46f3 100644
--- a/boards/arm/mimxrt1050_evk/pinmux.c
+++ b/boards/arm/mimxrt1050_evk/pinmux.c
@@ -151,11 +151,24 @@ static int mimxrt1050_evk_init(struct device *dev)
 
 	/* pull up the ENET_INT before RESET. */
 	GPIO_WritePinOutput(GPIO1, 10, 1);
-	/* RESET PHY chip. */
-	GPIO_WritePinOutput(GPIO1, 9, 1);
+	GPIO_WritePinOutput(GPIO1, 9, 0);
 #endif
 
 	return 0;
 }
 
+#ifdef CONFIG_ETH_MCUX_0
+static int mimxrt1050_evk_phy_reset(struct device *dev)
+{
+	/* RESET PHY chip. */
+	k_busy_wait(10*USEC_PER_MSEC);
+	GPIO_WritePinOutput(GPIO1, 9, 1);
+
+	return 0;
+}
+#endif
+
 SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0);
+#ifdef CONFIG_ETH_MCUX_0
+SYS_INIT(mimxrt1050_evk_phy_reset, PRE_KERNEL_2, 0);
+#endif
diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c
index 36f828627af..d9864938216 100644
--- a/drivers/ethernet/eth_mcux.c
+++ b/drivers/ethernet/eth_mcux.c
@@ -107,11 +107,19 @@ struct eth_context {
 
 static void eth_0_config_func(void);
 
+#ifdef CONFIG_HAS_MCUX_CACHE
+static __nocache enet_rx_bd_struct_t __aligned(ENET_BUFF_ALIGNMENT)
+rx_buffer_desc[CONFIG_ETH_MCUX_RX_BUFFERS];
+
+static __nocache enet_tx_bd_struct_t __aligned(ENET_BUFF_ALIGNMENT)
+tx_buffer_desc[CONFIG_ETH_MCUX_TX_BUFFERS];
+#else
 static enet_rx_bd_struct_t __aligned(ENET_BUFF_ALIGNMENT)
 rx_buffer_desc[CONFIG_ETH_MCUX_RX_BUFFERS];
 
 static enet_tx_bd_struct_t __aligned(ENET_BUFF_ALIGNMENT)
 tx_buffer_desc[CONFIG_ETH_MCUX_TX_BUFFERS];
+#endif
 
 #if defined(CONFIG_PTP_CLOCK_MCUX)
 /* Packets to be timestamped. */
@@ -319,6 +327,7 @@ static void eth_mcux_phy_event(struct eth_context *context)
 			context->link_up = link_up;
 			context->phy_state = eth_mcux_phy_state_read_duplex;
 			net_eth_carrier_on(context->iface);
+			k_sleep(USEC_PER_MSEC);
 		} else if (!link_up && context->link_up) {
 			LOG_INF("Link down");
 			context->link_up = link_up;
diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_enet.c b/ext/hal/nxp/mcux/drivers/imx/fsl_enet.c
index b8bb27ea1ab..7e2a8e7dc96 100644
--- a/ext/hal/nxp/mcux/drivers/imx/fsl_enet.c
+++ b/ext/hal/nxp/mcux/drivers/imx/fsl_enet.c
@@ -885,6 +885,7 @@ static void ENET_SetRxBufferDescriptors(enet_handle_t *handle,
 static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId)
 {
     assert(ringId < FSL_FEATURE_ENET_QUEUE);
+    __DSB();
 
     switch (ringId)
     {
@@ -1476,6 +1477,8 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint3
         handle->rxBdCurrent[ringId]++;
     }
 
+    __DSB();
+
     /* Actives the receive buffer descriptor. */
     switch (ringId)
     {
diff --git a/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c b/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c
index b8bb27ea1ab..9871d418839 100644
--- a/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c
+++ b/ext/hal/nxp/mcux/drivers/kinetis/fsl_enet.c
@@ -885,6 +885,7 @@ static void ENET_SetRxBufferDescriptors(enet_handle_t *handle,
 static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId)
 {
     assert(ringId < FSL_FEATURE_ENET_QUEUE);
+    __DSB();
 
     switch (ringId)
     {
@@ -1476,6 +1477,7 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint3
         handle->rxBdCurrent[ringId]++;
     }
 
+    __DSB();
     /* Actives the receive buffer descriptor. */
     switch (ringId)
     {