From 05d1c3a7f061352b807bf180ca925c7cc035d4f6 Mon Sep 17 00:00:00 2001 From: Shaunak saha Date: Mon, 16 Jun 2025 11:36:53 -0700 Subject: [PATCH] boards: mps4: Add initial support for corstone315 What is changed? - Add initial support for the MPS4 Corstone-315 FVP platform, including board and SoC definitions.The qualifier to build/run application with board mps4/corstone315 is `mps4/corstone315/fvp` for secure and `mps3/corstone315/fvp/ns` for non-secure. - FVP testing with corstone315 uses the ARM FVP `FVP_Corstone_SSE-315`. Why do we need this change? - This enables FVP support for corstone315. - A separate FVP variant was added for corstone315 as the TFM board used for non-secure variant differs for FPGA and FVP. TFM board `arm/mps4/corstone315` support is present but no FVP support yet. We can test this by building TF-M with -DTFM_PLATFORM=arm/mps4/corstone315 and then lauching FVP: FVP_Corstone_SSE-315 --data "bl1_1.bin"@0x11000000 --data "cm_provisioning_bundle.bin"@0x12024000 --data "dm_provisioning_bundle.bin"@0x1202aa00 --data "bl2_signed.bin"@0x12031400 --data "tfm_s_ns_signed.bin"@0x38000000 Signed-off-by: Shaunak saha --- boards/arm/mps4/Kconfig.defconfig | 4 +- boards/arm/mps4/Kconfig.mps4 | 1 + boards/arm/mps4/board.cmake | 10 +- boards/arm/mps4/board.yml | 5 + boards/arm/mps4/mps4_corstone315_fvp.dts | 97 +++++++++++++++++ boards/arm/mps4/mps4_corstone315_fvp.yaml | 26 +++++ .../arm/mps4/mps4_corstone315_fvp_defconfig | 19 ++++ boards/arm/mps4/mps4_corstone315_fvp_ns.dts | 102 ++++++++++++++++++ boards/arm/mps4/mps4_corstone315_fvp_ns.yaml | 15 +++ .../mps4/mps4_corstone315_fvp_ns_defconfig | 19 ++++ soc/arm/mps4/Kconfig | 12 +++ .../mps4/Kconfig.defconfig.mps4_corstone315 | 9 ++ soc/arm/mps4/Kconfig.soc | 5 + soc/arm/soc.yml | 1 + 14 files changed, 320 insertions(+), 5 deletions(-) create mode 100644 boards/arm/mps4/mps4_corstone315_fvp.dts create mode 100644 boards/arm/mps4/mps4_corstone315_fvp.yaml create mode 100644 boards/arm/mps4/mps4_corstone315_fvp_defconfig create mode 100644 boards/arm/mps4/mps4_corstone315_fvp_ns.dts create mode 100644 boards/arm/mps4/mps4_corstone315_fvp_ns.yaml create mode 100644 boards/arm/mps4/mps4_corstone315_fvp_ns_defconfig create mode 100644 soc/arm/mps4/Kconfig.defconfig.mps4_corstone315 diff --git a/boards/arm/mps4/Kconfig.defconfig b/boards/arm/mps4/Kconfig.defconfig index b4e98775386..96cbd9472ea 100644 --- a/boards/arm/mps4/Kconfig.defconfig +++ b/boards/arm/mps4/Kconfig.defconfig @@ -1,7 +1,7 @@ # Copyright 2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 -if BOARD_MPS4_CORSTONE320_FVP +if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE320_FVP if SERIAL @@ -10,7 +10,7 @@ config UART_INTERRUPT_DRIVEN endif # SERIAL -if ROMSTART_RELOCATION_ROM && BOARD_MPS4_CORSTONE320_FVP +if ROMSTART_RELOCATION_ROM && (BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE320_FVP) config ROMSTART_REGION_ADDRESS default $(dt_nodelabel_reg_addr_hex,itcm) diff --git a/boards/arm/mps4/Kconfig.mps4 b/boards/arm/mps4/Kconfig.mps4 index ffb494cf337..46ce14cc062 100644 --- a/boards/arm/mps4/Kconfig.mps4 +++ b/boards/arm/mps4/Kconfig.mps4 @@ -3,4 +3,5 @@ config BOARD_MPS4 select SOC_SERIES_MPS4 + select SOC_MPS4_CORSTONE315 if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE315_FVP_NS select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS diff --git a/boards/arm/mps4/board.cmake b/boards/arm/mps4/board.cmake index 6497c65c426..4e5044ab1b7 100644 --- a/boards/arm/mps4/board.cmake +++ b/boards/arm/mps4/board.cmake @@ -7,10 +7,15 @@ # -if(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS) +if(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE315_FVP_NS) + set(SUPPORTED_EMU_PLATFORMS armfvp) + set(ARMFVP_BIN_NAME FVP_Corstone_SSE-315) +elseif(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS) set(SUPPORTED_EMU_PLATFORMS armfvp) set(ARMFVP_BIN_NAME FVP_Corstone_SSE-320) - if(CONFIG_BOARD_MPS4_CORSTONE320_FVP) +endif() + +if(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP) set(ARMFVP_FLAGS # default is '0x11000000' but should match cpu.INITSVTOR which is 0. -C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0 @@ -19,7 +24,6 @@ if(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS) # few MPU tests to fail. -C mps4_board.subsystem.cpu0.MPU_S=16 ) - endif() endif() if(CONFIG_BUILD_WITH_TFM) diff --git a/boards/arm/mps4/board.yml b/boards/arm/mps4/board.yml index 8c2b411846f..760321039f6 100644 --- a/boards/arm/mps4/board.yml +++ b/boards/arm/mps4/board.yml @@ -3,6 +3,11 @@ board: full_name: MPS4 vendor: arm socs: + - name: 'corstone315' + variants: + - name: 'fvp' + variants: + - name: 'ns' - name: 'corstone320' variants: - name: 'fvp' diff --git a/boards/arm/mps4/mps4_corstone315_fvp.dts b/boards/arm/mps4/mps4_corstone315_fvp.dts new file mode 100644 index 00000000000..98c87ce7ed7 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp.dts @@ -0,0 +1,97 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps4-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram; + zephyr,flash = &isram; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@50004000 { + compatible = "arm,ethos-u"; + reg = <0x50004000>; + interrupts = <16 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@12000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x12000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(32)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 { /* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps4_common_soc_peripheral.dtsi" + }; + }; +}; + +#include "mps4_common.dtsi" diff --git a/boards/arm/mps4/mps4_corstone315_fvp.yaml b/boards/arm/mps4/mps4_corstone315_fvp.yaml new file mode 100644 index 00000000000..4af1421bcbc --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp.yaml @@ -0,0 +1,26 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps4/corstone315/fvp +name: Arm MPS4-Corstone315-FVP +type: mcu +arch: arm +ram: 2048 +flash: 4096 +simulation: + - name: armfvp + exec: FVP_Corstone_SSE-315 +toolchain: + - gnuarmemb + - zephyr +supported: + - gpio +testing: + default: true + timeout_multiplier: 4 + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps4/mps4_corstone315_fvp_defconfig b/boards/arm/mps4/mps4_corstone315_fvp_defconfig new file mode 100644 index 00000000000..26d5a732e49 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp_defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y +# ROMSTART_REGION address and size are defined in Kconfig.defconfig +CONFIG_ROMSTART_RELOCATION_ROM=y diff --git a/boards/arm/mps4/mps4_corstone315_fvp_ns.dts b/boards/arm/mps4/mps4_corstone315_fvp_ns.dts new file mode 100644 index 00000000000..cb5a38baf47 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp_ns.dts @@ -0,0 +1,102 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps4-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the non-secure addresses, if you add 0x10000000 + * you'll get the secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/HEAD/platform/ext/target/arm/mps4/common/partition/flash_layout.h + */ + + code: memory@28080000 { + reg = <0x28080000 DT_SIZE_K(512)>; + }; + + ram: memory@21020000 { + reg = <0x21020000 DT_SIZE_M(1)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps4_common_soc_peripheral.dtsi" + }; + }; +}; + +#include "mps4_common.dtsi" diff --git a/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml b/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml new file mode 100644 index 00000000000..01bee24100a --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml @@ -0,0 +1,15 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps4/corstone315/fvp/ns +name: Arm MPS4-Corstone315-FVP_ns +type: mcu +arch: arm +ram: 1024 +flash: 512 +toolchain: + - gnuarmemb + - zephyr +testing: + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps4/mps4_corstone315_fvp_ns_defconfig b/boards/arm/mps4/mps4_corstone315_fvp_ns_defconfig new file mode 100644 index 00000000000..d59d419011b --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp_ns_defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y +CONFIG_BUILD_WITH_TFM=y diff --git a/soc/arm/mps4/Kconfig b/soc/arm/mps4/Kconfig index 0054f715208..ea733d1566d 100644 --- a/soc/arm/mps4/Kconfig +++ b/soc/arm/mps4/Kconfig @@ -5,6 +5,17 @@ config SOC_SERIES_MPS4 select ARM select GPIO_MMIO32 if GPIO +config SOC_MPS4_CORSTONE315 + select CPU_CORTEX_M85 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARMV8_1_M_MVEI + select ARMV8_1_M_MVEF + select ARMV8_1_M_PMU + select ARM_MPU_PXN if ARM_MPU + config SOC_MPS4_CORSTONE320 select CPU_CORTEX_M85 select CPU_HAS_ARM_SAU @@ -18,4 +29,5 @@ config SOC_MPS4_CORSTONE320 config ARMV8_1_M_PMU_EVENTCNT int + default 8 if SOC_MPS4_CORSTONE315 default 8 if SOC_MPS4_CORSTONE320 diff --git a/soc/arm/mps4/Kconfig.defconfig.mps4_corstone315 b/soc/arm/mps4/Kconfig.defconfig.mps4_corstone315 new file mode 100644 index 00000000000..191b5d45df4 --- /dev/null +++ b/soc/arm/mps4/Kconfig.defconfig.mps4_corstone315 @@ -0,0 +1,9 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MPS4_CORSTONE315 + +config NUM_IRQS + default 232 + +endif diff --git a/soc/arm/mps4/Kconfig.soc b/soc/arm/mps4/Kconfig.soc index a557d287f0e..98087bb3676 100644 --- a/soc/arm/mps4/Kconfig.soc +++ b/soc/arm/mps4/Kconfig.soc @@ -10,9 +10,14 @@ config SOC_SERIES_MPS4 config SOC_SERIES default "mps4" if SOC_SERIES_MPS4 +config SOC_MPS4_CORSTONE315 + bool + select SOC_SERIES_MPS4 + config SOC_MPS4_CORSTONE320 bool select SOC_SERIES_MPS4 config SOC + default "corstone315" if SOC_MPS4_CORSTONE315 default "corstone320" if SOC_MPS4_CORSTONE320 diff --git a/soc/arm/soc.yml b/soc/arm/soc.yml index 2caf077656a..821da33e9cf 100644 --- a/soc/arm/soc.yml +++ b/soc/arm/soc.yml @@ -17,6 +17,7 @@ family: - name: corstone310 - name: mps4 socs: + - name: corstone315 - name: corstone320 - name: musca socs: