From 03cafbdaefeeddec0f0bd3ab61360ae6bf87d3dd Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Mon, 13 May 2024 17:38:53 -0700 Subject: [PATCH] arch/xtensa: "NMILEVEL" is an optional feature Some oddballs cores can be generated without an "NMI" interrupt, in which case core-isa.h will not define XCHAL_NMILEVEL. This code is trying to unconditionally mask interrupts, so XCHAL_EXCM_LEVEL is the pedantically correct choice anyway (NMI's by definition, cannot be masked). Signed-off-by: Andy Ross --- arch/xtensa/core/vector_handlers.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/core/vector_handlers.c b/arch/xtensa/core/vector_handlers.c index ee0ec0fe939..f0b0a9175ff 100644 --- a/arch/xtensa/core/vector_handlers.c +++ b/arch/xtensa/core/vector_handlers.c @@ -364,7 +364,7 @@ void *xtensa_excint1_c(int *interrupted_stack) * thread. */ __asm__ volatile("rsil %0, %1" - : "=r" (ignore) : "i"(XCHAL_NMILEVEL)); + : "=r" (ignore) : "i"(XCHAL_EXCM_LEVEL)); _current_cpu->nested = 1; }